公开(公告)号：JPH11214529A

公开(公告)日：1999-08-06

申请号：JP30387798

申请日：1998-10-26

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  BOLOGNESI DAVIDE ,  MARI ANGELO

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To make it possible to integrate a plurality of MOS devices of different voltage thresholds in one and the same substrate, by a method wherein when forming a plurality of channel regions for the MOS devices, impurities are selectively doped into a geometrical pattern with a gate electrode as a mask. SOLUTION: After a gate oxide film 3 and a polycrystalline silicon layer 4 are formed, these layers 3, 4 are selectively removed to form square openings for a transistor 1' and stripe openings for a transistor 1" to form a gate electrode 5, 5' for the transistor 1', 1". Then, with the gate electrode 5, 5' as a mask, P-type impurities are selectively doped into a drain layer 2 to form the main body region 7 of the transistor 1', 1". The main body region 7 has a square or stripe shape and is extended under the gate electrode 5, 5' to form a channel region of the transistor. Again, N-type impurities are selectively doped into the main body region 7 with the gate electrode 5, 5' as a mask to form a source region.

公开(公告)号：DE69531783D1

公开(公告)日：2003-10-23

申请号：DE69531783

申请日：1995-10-09

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRANCO GIOVANNI ,  CAMALLERI CATENO MARCO ,  FRISINA FERRUCCIO

IPC: H01L21/761 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06

Abstract: A construction method for power devices with deep edge ring, which has the particularity of comprising the following steps: (a) the growth of a lightly doped N-type epitaxial layer (20) on a heavily doped N-type substrate (10); (b) the growth of an oxide (30) on the upper portion of the epitaxial layer (20); (c) the masked implantation of boron ions (40); (d) an oxide etching to expose regions for aluminum ion implantation; (e) the growth of a layer of preimplantation oxide; (f) the masking of the body regions with a layer of photosensitive material (50) and the implantation of aluminum ions (60); and (g) a single thermal diffusion process for forming a layer of thermal oxide (70) above the epitaxial layer (20) and for simultaneously forming at least one deep aluminum ring (90) that is adjacent to the body region doped with boron (80).

公开(公告)号：DE69527146T2

公开(公告)日：2002-12-12

申请号：DE69527146

申请日：1995-11-10

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO

IPC: H01L27/02 ,  H01L29/78

Abstract: The device (10) presents a polysilicon layer (36) extending over a wafer (20) of semiconductor material, along the edge of the active region (34) of the device, and partly over a thick field oxide layer (35) which externally delimits the active region. The polysilicon layer (36) forms both a field-plate region (37) at its inner edge, and a Zener protection diode (11) over the field oxide layer (35), outwards of and contiguous to the field-plate region (37). The terminals of the diode (11) are respectively connected to the source metal region (30) and the gate metal region (44); the diode (11) therefore extends along the whole of the perimeter of the device (10), and presents an extensive junction area without greatly reducing the active area of the device.

公开(公告)号：DE69527146D1

公开(公告)日：2002-07-25

申请号：DE69527146

申请日：1995-11-10

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO

IPC: H01L27/02 ,  H01L29/78

Abstract: The device (10) presents a polysilicon layer (36) extending over a wafer (20) of semiconductor material, along the edge of the active region (34) of the device, and partly over a thick field oxide layer (35) which externally delimits the active region. The polysilicon layer (36) forms both a field-plate region (37) at its inner edge, and a Zener protection diode (11) over the field oxide layer (35), outwards of and contiguous to the field-plate region (37). The terminals of the diode (11) are respectively connected to the source metal region (30) and the gate metal region (44); the diode (11) therefore extends along the whole of the perimeter of the device (10), and presents an extensive junction area without greatly reducing the active area of the device.

公开(公告)号：IT1244119B

公开(公告)日：1994-07-05

申请号：IT2223790

申请日：1990-11-29

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  TAVOLO NELLA ,  RASPAGLIESI MARIO

IPC: H01L21/322 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L

公开(公告)号：JP2000183350A

公开(公告)日：2000-06-30

申请号：JP34835599

申请日：1999-12-08

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of an integrated edge structure for a high voltage semiconductor device. SOLUTION: A first conductivity-type (n-type) first semiconductor layer 41 is formed, and a first mask is formed on the upper face. A part of the mask is removed, and at least one opening is formed in the mask. Second conductivity- type impurities are introduced into the first semiconductor layer 41 through an opening, the first mask is completely removed and an N-type second semiconductor layer 42 is formed on the first semiconductor layer. The impurities implanted into the first semiconductor layer are diffused, and a P-type doped region 220 is formed in the first and second semiconductor layers. Final edge structure provided with plural N-type overlap semiconductor layers 41-46, and two inserted columns in plural overlap semiconductor layers formed of the overlap of plural P-type doped regions 220-260 implanted from the opening is formed by repeating six processes once or more. The column near the high- voltage semiconductor device is deeper than the column far from the device.

公开(公告)号：DE69531783T2

公开(公告)日：2004-07-15

申请号：DE69531783

申请日：1995-10-09

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRANCO GIOVANNI ,  CAMALLERI CATENO MARCO ,  FRISINA FERRUCCIO

IPC: H01L21/761 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06

Abstract: A construction method for power devices with deep edge ring, which has the particularity of comprising the following steps: (a) the growth of a lightly doped N-type epitaxial layer (20) on a heavily doped N-type substrate (10); (b) the growth of an oxide (30) on the upper portion of the epitaxial layer (20); (c) the masked implantation of boron ions (40); (d) an oxide etching to expose regions for aluminum ion implantation; (e) the growth of a layer of preimplantation oxide; (f) the masking of the body regions with a layer of photosensitive material (50) and the implantation of aluminum ions (60); and (g) a single thermal diffusion process for forming a layer of thermal oxide (70) above the epitaxial layer (20) and for simultaneously forming at least one deep aluminum ring (90) that is adjacent to the body region doped with boron (80).

公开(公告)号：DE69421606D1

公开(公告)日：1999-12-16

申请号：DE69421606

申请日：1994-03-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO

IPC: H01L29/73 ,  H01L21/22 ,  H01L21/331 ,  H01L29/732

Abstract: A manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time comprises the steps of: in a silicon material (1, 2), forming at least one bipolar transistor occupying a first area (AD) on a first surface of the silicon material (1, 2); covering the first surface of the silicon material (1, 2) with an insulating material layer (5); selectively removing the insulating material layer (5) to open at least one window (6) having a second area (APt) much smaller than the first area (AD) occupied by the bipolar transistor; implanting into the silicon material (1, 2) a medium dose (D) of platinum ions through said window (6); and diffusing into the silicon material (1, 2) the implanted platinum ions to obtain a uniform distribution of platinum inside the transistor.

公开(公告)号：DE69321966T2

公开(公告)日：1999-06-02

申请号：DE69321966

申请日：1993-12-24

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MANGIAGLI MARCANTONIO

IPC: H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

Abstract: An integrated structure pad assembly for lead bonding to a power semiconductor device chip comprises a chip portion having a top surface covered by a metallization layer (10) and which comprises a first sub-portion (1) wherein functionally active elements of the power device are present; said chip portion comprises at least one second sub-portion (11) wherein no functionally active elements of the power device are present, and a top surface of the metallization layer (10) is elevated over said at least one second sub-portion (11) with respect to the first sub-portion (1) to form at least one protrusion which forms a support surface for a lead.

公开(公告)号：DE69117889D1

公开(公告)日：1996-04-18

申请号：DE69117889

申请日：1991-11-16

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  TAVOLO NELLA ,  RASPAGLIESI MARIO

IPC: H01L21/322 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/167