公开(公告)号：JP2006075982A

公开(公告)日：2006-03-23

申请号：JP2005260722

申请日：2005-09-08

Applicant: Robert Bosch Gmbh ,  ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングRobert Bosch Gmbh

Inventor： BENZEL HUBERT ,  FINKBEINER STEFAN DR ,  ILLING MATTHIAS ,  SCHAEFER FRANK ,  ARMBRUSTER SIMON ,  LAMMEL GERHARD ,  SCHELLING CHRISTOPH ,  BRASAS JOERG

IPC: B81C1/00 ,  B81B3/00 ,  G01P15/00 ,  H01L29/84

CPC classification number: B81C1/00047 ,  B81B2203/0109 ,  B81C2201/0115 ,  B81C2201/0116 ,  G01L9/0045

Abstract: PROBLEM TO BE SOLVED: To form a diaphragm or a hollow chamber with a slight thickness error.
SOLUTION: A structured etching mask 210 with a large number of holes is attached to a semiconductor substrate 200, and recesses 220 are formed below the holes by an etching process. A porous region 270 is formed by anodization below at least one recess provided in the semiconductor substrate, and a grated structure part 280 is formed by anodization between the recesses in the surface of the semiconductor substrate formed of a non-porous substrate material. The etching mask is removed, and the hollow chamber is formed by thermal treatment or electrolytic polishing of the semiconductor substrate from at least one porous region, and the diaphragm is formed above the hollow chamber by thermal treatment or electrolytic polishing of the semiconductor substrate from the grated structure part.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：形成具有轻微厚度误差的隔膜或中空室。 解决方案：具有大量孔的结构化蚀刻掩模210附着到半导体衬底200上，并且通过蚀刻工艺在孔的下方形成凹部220。 多孔区域270通过在半导体衬底中设置的至少一个凹部下方进行阳极氧化而形成，并且通过在由无孔基底材料形成的半导体衬底的表面中的凹部之间的阳极氧化来形成磨细结构部分280。 除去蚀刻掩模，并且通过从至少一个多孔区域对半导体衬底进行热处理或电解抛光来形成中空室，并且通过半导体衬底的热处理或电解抛光从中空室上形成隔膜 磨碎结构部分。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：US12022270B2

公开(公告)日：2024-06-25

申请号：US17761669

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiale Su ,  Guoping Zhou ,  Xinwei Zhang ,  Changfeng Xia

IPC: H04R19/04 ,  B81C1/00 ,  H04R31/00

CPC classification number: H04R31/003 ,  B81C1/00158 ,  H04R19/04 ,  B81C2201/0105 ,  B81C2201/0116 ,  B81C2201/0133 ,  H04R2201/003

Abstract: A preparation method for a micro-electromechanical systems (MEMS) microphone includes the steps of: providing a silicon substrate having a silicon surface; forming an enclosed cavity in the silicon substrate; forming a plurality of spaced apart acoustic holes in the silicon substrate, each acoustic hole having two openings, one of which communicating with the cavity and the other one located on the silicon surface; forming a sacrificial layer on the silicon substrate, which includes a first filling portion, a second filling portion and a shielding portion; forming a polysilicon layer on the shielding portion; forming a recess in the silicon substrate on the side away from the silicon surface; and removing the first filling portion, the second filling portion and part of the shielding portion so that the recess is brought into communication with the cavity to form a back chamber, and that the polysilicon layer, the remainder of the shielding portion and the silicon substrate together delimit a hollow chamber, the hollow chamber communicating with the opening of the plurality of acoustic holes away from the cavity, completing the MEMS microphone.

公开(公告)号：US20230375416A1

公开(公告)日：2023-11-23

申请号：US18228333

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsai-Hao HUNG ,  Shih-Chi KUO

IPC: G01K7/32 ,  B81C1/00 ,  B81B3/00

CPC classification number: G01K7/32 ,  B81C1/00944 ,  B81B3/0008 ,  B81B2203/0136 ,  B81C2201/0105 ,  B81C2201/013 ,  B81C2201/0116 ,  B81B2201/0278 ,  B81B2203/04

Abstract: The structure of a micro-electro-mechanical system (MEMS) thermal sensor and a method of fabricating the MEMS thermal sensor are disclosed. A method of fabricating a MEMS thermal sensor includes forming first and second sensing electrodes with first and second electrode fingers, respectively, on a substrate and forming a patterned layer with a rectangular cross-section between a pair of the first electrode fingers. The first and second electrode fingers are formed in an interdigitated configuration and suspended above the substrate. The method further includes modifying the patterned layer to have a curved cross-section between the pair of the first electrode fingers, forming a curved sensing element on the modified patterned layer to couple to the pair of the first electrodes, and removing the modified patterned layer.

公开(公告)号：US20190233280A1

公开(公告)日：2019-08-01

申请号：US16213019

申请日：2018-12-07

Applicant: Shenyang Silicon Technology Co., Ltd.

Inventor： Xiang LI

IPC: B81C1/00 ,  B81B1/00

CPC classification number: B81C1/00047 ,  B08B3/08 ,  B32B37/06 ,  B32B38/0008 ,  B32B43/006 ,  B32B2038/0016 ,  B32B2310/14 ,  B32B2313/00 ,  B32B2457/14 ,  B81B1/004 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00357 ,  B81C1/00507 ,  B81C1/00849 ,  B81C2201/0116 ,  B81C2201/0125 ,  B81C2201/0178 ,  B81C2201/019 ,  B81C2201/0192 ,  B81C2201/0194

Abstract: A method for processing a silicon wafer with a through cavity structure. The method is operated in accordance with the following sequence: performing ion implantation on a silicon wafer or pattern wafer; implanting a dummy substrate; bonding the silicon wafer to the pattern wafer; performing grinding and polishing, and thinning the pattern wafer to a depth exposing the pattern; bonding; and peeling the dummy substrate. Compared with the prior art, the present invention is standard in operation, and the product quality can be effectively guaranteed. The product has high cost performance and excellent comprehensive technical effect. The present invention has expectable relatively large economic values and social values.

公开(公告)号：US20190152772A1

公开(公告)日：2019-05-23

申请号：US16091384

申请日：2017-04-06

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS) ,  UNIVERSITÉ DE TOURS

Inventor： Daniel ALQUIER ,  Rami KHAZAKA ,  Jean François MICHAUD ,  Marc PORTAIL

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B2201/0214 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C1/00476 ,  B81C2201/0116

Abstract: A process for fabricating a micromechanical structure made of silicon carbide including a cavity, from a stack including a first silicon-carbide layer and a silicon layer on the first silicon-carbide layer, the process including shaping the silicon layer so as to form a discrete silicon structure on the first silicon-carbide layer. The process further includes, after the shaping of the silicon layer, a carbonization to initiate the removal of the discrete silicon structure; depositing a second silicon-carbide layer; and an annealing step, the discrete silicon structure being entirely removed at the end of the annealing.

公开(公告)号：US20170287772A1

公开(公告)日：2017-10-05

申请号：US15630579

申请日：2017-06-22

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch ,  Alessia Scire ,  Steffen Bieselt

IPC: H01L21/764 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  B81C1/00 ,  H01L21/324 ,  H01L27/12

CPC classification number: H01L21/764 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C2201/0116 ,  H01L21/3247 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7833

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate.

公开(公告)号：US08921974B2

公开(公告)日：2014-12-30

申请号：US13911106

申请日：2013-06-06

Applicant: Infineon Technologies AG

Inventor： Thoralf Kautzsch ,  Boris Binder ,  Uwe Rudolph ,  Frank Hoffman

IPC: H01L29/00 ,  H01L21/76 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00626 ,  B81B3/0021 ,  B81B2203/0109 ,  B81B2203/0315 ,  B81C1/00182 ,  B81C2201/0116

Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

Abstract translation: 描述和描述了与半导体制造有关的实施例和具有半导体结构的半导体器件

公开(公告)号：US08716050B2

公开(公告)日：2014-05-06

申请号：US13721496

申请日：2012-12-20

Applicant: The Hong Kong University of Science and Technology

Inventor： Man Wong ,  Fan Zeng

IPC: H01L21/00 ,  H01L29/82

CPC classification number: H01L21/461 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00822 ,  B01J2219/00828 ,  B01J2219/00837 ,  B01J2219/0086 ,  B01L3/502707 ,  B01L2300/0816 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C1/00071 ,  B81C2201/0116 ,  B81C2201/0178 ,  H01L29/16

Abstract: Described herein is a microchannel that is formed beneath and parallel to a surface of a silicon substrate. Silicon migration technology is utilized to form a microchannel that is buried beneath the surface of the silicon substrate. Etching opens at least one end of the microchannel. Oxidization is utilized through the open end of the microchannel to facilitate a controlled diameter of the microchannel.

Abstract translation: 这里描述的是形成在硅衬底的表面下方并平行于其的表面的微通道。 利用硅迁移技术形成埋在硅衬底表面下方的微通道。 蚀刻打开微通道的至少一端。 通过微通道的开口端利用氧化，以促进微通道的受控直径。

公开(公告)号：US20140097521A1

公开(公告)日：2014-04-10

申请号：US13648170

申请日：2012-10-09

Applicant: INFINEON TECHNOLOGIES DRESDEN GMBH

Inventor： Thoralf Kautzsch ,  Alessia Scire ,  Steffen Bieselt

IPC: H01L29/02 ,  H01L21/26 ,  H01L21/302

CPC classification number: H01L21/764 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C2201/0116 ,  H01L21/3247 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7833

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底内形成第一空腔。 第一空腔设置在基板的一部分下方。 该方法还包括在第一腔内形成第一支柱以支撑衬底的该部分。

公开(公告)号：US20100187572A1

公开(公告)日：2010-07-29

申请号：US12360079

申请日：2009-01-26

Applicant: Hans S. Cho ,  Theodore I. Kamins

Inventor： Hans S. Cho ,  Theodore I. Kamins

IPC: H01L29/267 ,  H01L21/20

CPC classification number: H01L29/0657 ,  B81C1/00142 ,  B81C1/00158 ,  B81C2201/0116 ,  H01L21/0237 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/764

Abstract: Methods of fabricating a suspended mono-crystalline structure use annealing to induce surface migration and cause a surface transformation to produce the suspended mono-crystalline structure above a cavity from a heteroepitaxial layer provided on a crystalline substrate. The methods include forming a three dimensional (3-D) structure in the heteroepitaxial layer where the 3-D structure includes high aspect ratio elements. The 3-D structure is annealed at a temperature below a melting point of the heteroepitaxial layer. The suspended mono-crystalline structure may be a portion of a semiconductor-on-nothing (SON) substrate.

Abstract translation: 制备悬浮的单晶结构的方法使用退火以诱导表面迁移并引起表面转变，从在提供于晶体衬底上的异质外延层的空腔上产生悬浮的单晶结构。 所述方法包括在异质外延层中形成三维（3-D）结构，其中3-D结构包括高纵横比元素。 3-D结构在异质外延层的熔点以下的温度下退火。 悬浮的单晶结构可以是无半导体（SON）衬底的一部分。