公开(公告)号：US06770569B2

公开(公告)日：2004-08-03

申请号：US10210315

申请日：2002-08-01

Applicant: Juergen A. Foerstner ,  Steven M. Smith ,  Raymond Mervin Roop

Inventor： Juergen A. Foerstner ,  Steven M. Smith ,  Raymond Mervin Roop

IPC: H01L2131

CPC classification number: B81C1/0038 ,  B81B2201/018 ,  B81B2201/0292 ,  B81C1/00246 ,  B81C2201/0164 ,  B81C2203/0735 ,  H01G5/18

Abstract: A method is provided for making a MEMS structure (69). In accordance with the method, a CMOS substrate (51) is provided which has interconnect metal (53) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.

Abstract translation: 提供了一种用于制造MEMS结构（69）的方法。 根据该方法，提供具有沉积在其上的互连金属（53）的CMOS基板（51）。 通过等离子体辅助化学气相沉积（PACVD）在由硅和硅 - 锗合金组成的组中选择的材料在衬底上产生MEMS结构。 使用PACVD的低沉积温度允许这些材料用于集成CMOS工艺后端的MEMS制造。

公开(公告)号：US06661070B2

公开(公告)日：2003-12-09

申请号：US10193804

申请日：2002-07-11

Applicant: Andrew J. Zosel ,  Joel A. Kubby ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Jingkuang Chen ,  Alex T. Tran

Inventor： Andrew J. Zosel ,  Joel A. Kubby ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Jingkuang Chen ,  Alex T. Tran

IPC: H01L2982

CPC classification number: B81C1/00666 ,  B81B2203/058 ,  B81C2201/014 ,  B81C2201/0164 ,  B81C2201/056 ,  G02B26/0833

Abstract: The present invention provides a micromechanical or microoptomechanical structure. The structure is produced by a process comprising defining a structure on a single crystal silicon layer separated by an insulator layer from a substrate layer; depositing and etching a polysilicon layer on the single crystal silicon layer, with remaining polysilcon forming mechanical or optical elements of the structure; exposing a selected area of the single crystal silicon layer; and releasing the formed structure.

公开(公告)号：US20030138588A1

公开(公告)日：2003-07-24

申请号：US10334588

申请日：2002-12-30

Inventor： Cleopatra Cabuz ,  Max C. Glenn ,  Francis M. Erdmann ,  Robert D. Horning

IPC: B32B009/00

CPC classification number: B81C1/00365 ,  B81C2201/0164 ,  Y10T428/21 ,  Y10T428/2495

Abstract: Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.

Abstract translation: 公开了具有减小的平面外曲率的硼掺杂硅层。 这些层在顶部和底部表面附近具有基本相等的硼浓度。 由于相反的浓度基本相等，所以层上的压缩应力基本平衡，从而导致具有减小的面外曲率的层。

公开(公告)号：US20030124761A1

公开(公告)日：2003-07-03

申请号：US10263623

申请日：2002-10-03

Inventor： Kris Baert ,  Matty Caymax ,  Cristina Rusu ,  Sherif Sedky ,  Ann Witvrouw

IPC: H01L021/00

CPC classification number: H01L31/1804 ,  B81C1/00666 ,  B81C2201/0164 ,  B81C2201/017 ,  C23C16/22 ,  G01J5/20 ,  H01L31/09 ,  Y02E10/547 ,  Y02P70/521

Abstract: Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1nullx layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.

Abstract translation: 获得沉积的多晶和低应力SiGe层的方法和设备。 这些层可以用于微机电系统（MEMS）装置或微加工结构中。 分析影响多晶层中的应力的不同参数。 参数包括但不限于：沉积温度; 半导体的浓度（例如，SixGe1-x层中的硅和锗的浓度，x是浓度参数）; 掺杂剂的浓度（例如硼或磷的浓度）; 压力量; 并使用等离子体。 取决于多晶SiGe生长的特定环境，可以使用不同的参数值。

公开(公告)号：US06503775B2

公开(公告)日：2003-01-07

申请号：US09956799

申请日：2001-09-21

Applicant: Satoru Nomoto ,  Masayoshi Takeuchi ,  Shuji Noda

Inventor： Satoru Nomoto ,  Masayoshi Takeuchi ,  Shuji Noda

IPC: H01L2100

CPC classification number: B81C1/00611 ,  B81C1/00365 ,  B81C2201/0122 ,  B81C2201/0164

Abstract: A production method of a micromachine includes a polysilicon film forming step which overlays grooves, defined in an upper surface of a sacrificial layer on a silicon substrate, with polysilicon layer so as to be flat. The production method includes a first processing step for filling the grooves by adding a lower laid portion of the polysilicon layer onto a sacrificial layer. The lower laid portion has a thickness greater than 0.625 times relative to a width of the grooves. The production method of the micromachine further includes a second processing step for making the polysilicon layer to have a predetermined thickness by adding a upper laid portion of the polysilicon layer on the lower laid portion to form the polysilicon layer, the upper laid portion formed by depositing polysilicon which has the same impurity concentration as the lower laid portion does.

公开(公告)号：WO2008124595A2

公开(公告)日：2008-10-16

申请号：PCT/US2008059415

申请日：2008-04-04

Applicant: ANALOG DEVICES INC ,  NUNAN THOMAS KIERAN

Inventor： NUNAN THOMAS KIERAN

IPC: B81C1/00

CPC classification number: B81C1/00666 ,  B81B2201/025 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0169

Abstract: A method of forming a thick polysilicon layer for a MEMS inertial sensor includes forming a first amorphous polysilicon film on a substrate in an elevated temperature environment for a period of time such that a portion of the amorphous polysilicon film undergoes crystallization and grain growth at least near the substrate. The method also includes forming an oxide layer on the first amorphous polysilicon film, annealing the first amorphous polysilicon film in an environment of about 1100°C or greater to produce a crystalline film, and removing the oxide layer. Lastly, the method includes forming a second amorphous polysilicon film on a surface of the crystalline polysilicon film in an elevated temperature environment for a period of time such that a portion of the second amorphous polysilicon film undergoes crystallization and grain growth at least near the surface of the crystalline polysilicon film.

Abstract translation: 形成用于MEMS惯性传感器的厚多晶硅层的方法包括在高温环境中在衬底上形成第一非晶多晶硅膜一段时间，使得非晶多晶硅膜的一部分经历结晶并且晶粒生长至少接近 底物。 该方法还包括在第一非晶多晶硅膜上形成氧化物层，在约1100℃或更高的环境中退火第一非晶多晶硅膜以产生结晶膜，并除去氧化物层。 最后，该方法包括在高温环境下在晶体多晶硅膜的表面上形成第二非晶多晶硅膜一段时间，使得第二非晶多晶硅膜的一部分在至少在表面附近发生结晶和晶粒生长 晶体多晶硅膜。

公开(公告)号：WO2002098788A2

公开(公告)日：2002-12-12

申请号：PCT/US2002/017216

申请日：2002-06-04

Applicant: HONEYWELL INTERNATIONAL INC.

Inventor： HORNING, Robert, D. ,  BURNS, David, W.

IPC: B81B3/00

CPC classification number: B81C1/00595 ,  B81B2201/0264 ,  B81C2201/0164

Abstract: A method of making a silicon micromechanical structure, from a lightly doped silicon substrate having less than 19 cm -3 boron therein. A p+ layer having a boron content of greater than 7 x 10 19 cm -3 and a germanium content of about 1 x 10 21 cm -3 is placed on the substrate. A mask is formed on the second side, followed by etching to the p+ layer. An insulator is put on the p+ layer and an electronic component is fabricated thereon. Preferred micromechanical structures are pressure sensors, cantilevered accelerometers, and dual web biplane accelerometers. Preferred electronic components are dielectrically isolated piezoresistors and resonant microbeams. The method may include the step of forming a lightly doped layer on the p+ layer to form a buried p+ layer prior to etching.

Abstract translation: 从其中具有小于5×10 19 cm 3的硼的轻掺杂硅衬底制造硅微机械结构的方法。 具有大于7×10 19 cm -3的硼含量和约1×10 21 cm -3的锗含量的p +层被放置在衬底上。 在第二面上形成掩模，然后蚀刻到p +层。 将绝缘体放在p +层上，并在其上制造电子部件。 优选的微机械结构是压力传感器，悬臂加速度计和双网双平面加速度计。 优选的电子部件是介电离子压敏电阻器和共振微束。 该方法可以包括在p +层上形成轻掺杂层以在蚀刻之前形成掩埋的p +层的步骤。

公开(公告)号：WO02012115A2

公开(公告)日：2002-02-14

申请号：PCT/US2001/024723

申请日：2001-08-07

IPC: B81B3/00 ,  B81C1/00 ,  H01L21/308 ,  H01L29/84 ,  B81B

CPC classification number: B81C1/00365 ,  B81C2201/0164 ,  Y10T428/21 ,  Y10T428/2495

Abstract: Layers of boron-doped silicon (36) having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near th etop (38) and bottom (40) surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers (36) are substantially balanced, thereby resulting in layers (36) with reduced out-of-plane curvature.

Abstract translation: 公开了具有减小的平面外曲率的硼掺杂硅（36）的层。 这些层在顶部（38）和底部（40）表面附近具有基本相等的硼浓度。 由于相反的浓度基本上相等，所以层（36）上的压缩应力基本平衡，从而导致具有降低的平面外曲率的层（36）。

公开(公告)号：WO2004013039A2

公开(公告)日：2004-02-12

申请号：PCT/US2003/014930

申请日：2003-05-13

Applicant: MOTOROLA, INC.

Inventor： FOERSTNER, Juergen, A. ,  SMITH, Steven, M. ,  ROOP, Raymond, Mervin

IPC: B81C1/00

CPC classification number: B81C1/0038 ,  B81B2201/018 ,  B81B2201/0292 ,  B81C1/00246 ,  B81C2201/0164 ,  B81C2203/0735 ,  H01G5/18

Abstract: A method is provided for making a MEMS structure (69). In accordance with the method, a CMOS substrate (51) is provided which has interconnect metal (53) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.

Abstract translation: 提供了一种用于制造MEMS结构（69）的方法。 根据该方法，提供具有沉积在其上的互连金属（53）的CMOS基板（51）。 通过等离子体辅助化学气相沉积（PACVD）在由硅和硅 - 锗合金组成的组中选择的材料在衬底上产生MEMS结构。 使用PACVD的低沉积温度允许这些材料用于集成CMOS工艺后端的MEMS制造。

公开(公告)号：WO2002103808A1

公开(公告)日：2002-12-27

申请号：PCT/JP2001/004979

申请日：2001-06-13

Applicant: 三菱電機株式会社 ,  石橋清志 ,  堀川牧夫 ,  奥村美香 ,  青砥正明 ,  吉田大作 ,  高倉博文

Inventor： 石橋清志 ,  堀川牧夫 ,  奥村美香 ,  青砥正明 ,  吉田大作 ,  高倉博文

IPC: H01L29/84

CPC classification number: B81C1/00666 ,  B81B2201/0235 ,  B81C2201/0164 ,  B81C2201/0169 ,  G01P15/125 ,  G01P2015/0814 ,  H01G4/33 ,  H01G5/16

Abstract: A thin−film structure manufactured by a semiconductor processing technique and a method for manufacturing the same, especially a thin−film structure constituting a semiconductor acceleration sensor and a method for manufacturing the same, wherein the stress in a thin−film body can be simply controlled, and the thickness of the thin−film body can be easily increased. A thin−film body (8) constituting each of a mass body (3), a beam (7), and a fixed electrode (5) of a semiconductor acceleration sensor is composed of doped polysilicon thin films (33, 35) formed by repeating the step of forming a polysilicon film while doping the film with, e.g., phosphorus as impurity.

Abstract translation: 通过半导体处理技术制造的薄膜结构及其制造方法，特别是构成半导体加速度传感器的薄膜结构及其制造方法，其中薄膜体中的应力可以简单地 可以容易地增加薄膜体的厚度。 构成半导体加速度传感器的质量体（3），光束（7）和固定电极（5）的薄膜体（8）由掺杂的多晶硅薄膜（33,35） 在用例如磷作为杂质掺杂膜的同时重复形成多晶硅膜的步骤。