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    Semiconductor device manufacturing method and semiconductor device
    42.
    发明专利
    Semiconductor device manufacturing method and semiconductor device 审中-公开
    半导体器件制造方法和半导体器件

    公开(公告)号：JP2013251358A

    公开(公告)日：2013-12-12

    申请号：JP2012124120

    申请日：2012-05-31

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： TSUCHIAKI MASAKATSU

    IPC: H01L21/3205 ,  C23C14/06 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/532 ,  H01L27/105 ,  H01L27/115 ,  H01L45/00 ,  H01L49/00

    CPC classification number: H01L21/76889 ,  H01L21/76885 ,  H01L23/53204 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method of forming a fine wiring pattern uniformly and stably; and provide a semiconductor device.SOLUTION: A semiconductor device manufacturing method according to an embodiment comprises: forming, on an insulation base material, first support parts each having lateral faces rising from a surface of the insulation base material; forming first coating films of amorphous silicon on the lateral faces of each first support part; burying first insulation films in between the first coating films and planarizing a surface of the first insulation films to expose the first coating films from the surface; and making the amorphous silicon of the first coating films into silicide to form first wiring.

    Abstract translation: 要解决的问题：提供均匀且稳定地形成精细布线图案的半导体器件制造方法; 并提供半导体器件。解决方案：根据实施例的半导体器件制造方法包括：在绝缘基材上形成各自具有从所述绝缘基材的表面起伏的侧面的第一支撑部; 在每个第一支撑部分的侧面上形成非晶硅的第一涂膜; 将第一绝缘膜埋在第一涂膜之间并平面化第一绝缘膜的表面以从表面露出第一涂膜; 并将第一涂膜的非晶硅制成硅化物以形成第一布线。

    薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
    44.
    发明申请
    薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法 审中-公开

    公开(公告)号：WO2016037373A1

    公开(公告)日：2016-03-17

    申请号：PCT/CN2014/086620

    申请日：2014-09-16

    Applicant: 深圳市华星光电技术有限公司

    Inventor： 柴立 ,  张晓星

    IPC: G02F1/133

    CPC classification number: H01L27/124 ,  G02F2001/136254 ,  H01L22/32 ,  H01L23/53204 ,  H01L27/1255 ,  H01L27/1259

    Abstract: 一种薄膜晶体管阵列基板（10）及薄膜晶体管阵列基板（10）的制备方法。所述薄膜晶体管阵列基板（10）包括：多个第一金属线（110），相邻的第一金属线（110）之间设置第一间隙（111）；多个第二金属线（120），相邻的第二金属线（120）之间设置第二间隙（121），所述第二金属线（120）与所述第一金属线（110）交叉设置以形成多个重叠部（113）；第一绝缘层（130），层叠设置在所述第一金属线（110）与所述第二金属线（120）之间，用于使所述第一金属线（110）与所述第二金属线（120）之间绝缘；第二绝缘层（140），覆盖在所述第二金属线（120）上，且与所述第二金属线（120）层叠设置；透明导电膜（150），覆盖在所述第二绝缘层（140）上。

    INTEGRATED PASSIVE DEVICES FORMED BY DEMASCENE PROCESSING
    46.
    发明申请
    INTEGRATED PASSIVE DEVICES FORMED BY DEMASCENE PROCESSING 审中-公开
    通过加速加工形成的集成无源器件

    公开(公告)号：WO2003058715A1

    公开(公告)日：2003-07-17

    申请号：PCT/US2002/037951

    申请日：2002-11-25

    Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.

    Inventor： VAN BUSKIRK, Peter, C.

    IPC: H01L23/48

    CPC classification number: H01L27/0805 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53204 ,  H01L27/222 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A passive transmission line element “device” monolithically integrated into an integrated circuit at one or more levels of the integrated circuit by using a damascene process to delineate a conductive line (30) such that at least the bottom surface and sidewalls of the conductive line are embedded in an enhancement layer (26) having high permeability and/or high permitivity. Optionally a second enhancement layer (34) may cover the conductive line, to completely embed or surround the conductive line with permeability and/or permitivity enhancement material. The passive transmission line device comprising the conductive line and the enhancement layer thus has enhanced distributed inductance and/or enhanced distributed capacitance. In addition, the passive transmission line device may optionally have enhanced distributed resistance as well by forming the conductive line from resistive “i.e., not highly conductive” material.

    Abstract translation: 一种无源传输线元件“器件”，其通过使用镶嵌工艺来描绘导线（30）而在集成电路的一个或多个层级上单片集成到集成电路中，使得至少导电线的底表面和侧壁为 嵌入在具有高磁导率和/或高介电常数的增强层（26）中。 可选地，第二增强层（34）可以覆盖导电线，从而用导电性和/或吸收增强材料完全嵌入或围绕导电线。 因此，包括导线和增强层的无源传输线装置具有增强的分布电感和/或增强的分布电容。 此外，无源传输线装置还可以通过从电阻性“即不是高导电性”的材料形成导电线，可选地具有增强的分布电阻。

    SEMICONDUCTOR DEVICE
    47.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：EP3208846A1

    公开(公告)日：2017-08-23

    申请号：EP17156454.5

    申请日：2003-07-24

    Applicant: Socionext Inc.

    Inventor： Watanabe, Kenichi

    IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58

    CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: There is provided a semiconductor device comprising: a rectangular semiconductor substrate that includes four corners; a first interconnection formed above the rectangular semiconductor substrate; a guard ring that includes a plurality of first groove-shaped vias formed above the first interconnection; and a second interconnection formed above the plurality of first groove-shaped vias, wherein: the first interconnection includes copper; the first groove-shaped vias include copper; the second interconnection includes copper; the plurality of first groove-shaped vias are integral with the second interconnection; the plurality of first groove-shaped vias are connected to the first interconnection; and each of the plurality of first groove-shaped vias includes a first pattern bent twice each time at an inner angle of 135 degrees at each of the four corners in a plan view and bent totally at 90 degrees at each of the four corners in a plan view.

    Abstract translation: 提供了一种半导体器件，包括：包括四个角的矩形半导体衬底; 形成在矩形半导体衬底上方的第一互连; 保护环，其包括形成在第一互连上方的多个第一槽形通孔; 以及形成在所述多个第一槽形通孔上方的第二互连，其中：所述第一互连包括铜; 第一槽形通孔包括铜; 第二互连包括铜; 所述多个第一凹槽形通孔与所述第二互连形成整体; 多个第一槽形通孔连接到第一互连; 并且所述多个第一槽形通路中的每一个包括第一图案，所述第一图案在平面图中在每个角处以135度的内角每次弯曲两次，并且在所述四个角处的每一个处以90度完全弯曲 平面图。

    Semiconductor device
    49.
    发明公开
    Semiconductor device 有权
    半导体器件

    公开(公告)号：EP2863430A2

    公开(公告)日：2015-04-22

    申请号：EP15150440.4

    申请日：2003-07-24

    Applicant: Fujitsu Semiconductor Limited

    Inventor： Watanabe, Kenichi

    IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/528

    CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: There is provided a semiconductor device comprising: a substrate; a first insulating film formed on the substrate; an aluminum layer formed above the first insulating film; a first guard ring which includes a first groove-shaped via-hole formed in the first insulating film and a first conductor formed in the first groove-shaped via-hole, the first conductor being connected to the substrate; and a second guard ring which includes a second groove-shaped via-hole formed in the first insulating film and a second conductor formed in the second groove-shaped via-hole, the second conductor being connected to the substrate. The second guard ring is surrounded by the first guard ring in a plan view, and the first guard ring is connected to the aluminum layer. Each of the first groove-shaped via-hole and the second groove-shaped via-hole includes a pattern bent twice each time at an inner angle of larger than 90 degree at each of four corners of the semiconductor device in a plan view.

    Abstract translation: 提供了一种半导体器件，包括：衬底; 形成在基板上的第一绝缘膜; 在第一绝缘膜上形成的铝层; 第一保护环，其包括形成在所述第一绝缘膜中的第一槽形通孔和形成在所述第一槽形通孔中的第一导体，所述第一导体连接到所述基板; 以及第二保护环，其包括形成在所述第一绝缘膜中的第二槽形通孔和形成在所述第二槽形通孔中的第二导体，所述第二导体连接到所述衬底。 第二保护环在平面图中由第一保护环包围，并且第一保护环连接至铝层。 第一槽形通孔和第二槽形通孔中的每一个均包括在平面图中在半导体器件的四个角部中的每一个处以大于90度的内角每次弯曲两次的图案。

    Semiconductor device and method for fabricating the same
    50.
    发明公开
    Semiconductor device and method for fabricating the same 有权
    Halbleitervorrichtung

    公开(公告)号：EP2175487A2

    公开(公告)日：2010-04-14

    申请号：EP10000804.4

    申请日：2003-07-24

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Watanabe, Kenichi

    IPC: H01L23/522 ,  H01L23/532

    CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

    Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此防止了埋入导体的缺陷填充，可以防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

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