公开(公告)号：WO2021221933A1

公开(公告)日：2021-11-04

申请号：PCT/US2021/027788

申请日：2021-04-16

Applicant: QUALCOMM INCORPORATED

Inventor： YEON, Jaehyun ,  HWANG, Suhyung ,  KUMAR, Rajneesh ,  HAN, Jeahyeong

IPC: H05K1/18 ,  H05K3/34

Abstract: A device that includes a flexible printed circuit board (PCB), a package coupled to the flexible PCB, a first antenna device coupled to the flexible PCB, and a second antenna device coupled to the flexible PCB. The first antenna device is configured to transmit and receive a first signal having a first frequency. The second antenna device is configured to transmit and receive a second signal having a second frequency. The first antenna device may be coupled to a second surface of the flexible PCB, and the second antenna device is coupled to the second surface of the flexible PCB. The first antenna device may be coupled to a second surface of the flexible PCB, and the second antenna device is coupled to a first surface of the flexible PCB.

公开(公告)号：WO2021178156A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/019046

申请日：2021-02-22

Applicant: QUALCOMM INCORPORATED

Inventor： HAN, Jeahyeong ,  KUMAR, Rajneesh ,  HWANG, Suhyung ,  YEON, Jaehyun ,  TASSOUDJI, Mohammad Ali ,  JESSIE, Darryl Sheldon ,  GALINDE, Ameya

IPC: H01Q21/28 ,  H01Q1/22 ,  H05K1/02 ,  H05K3/46 ,  H01L23/552 ,  H01L23/66

Abstract: A device that includes a first substrate comprising a first antenna, an integrated device coupled to the first substrate, an encapsulation layer located over the first substrate and the integrated device, a second substrate comprising a second antenna, and a flexible connection coupled to the first substrate and the second substrate. The device includes a shield formed over a surface of the encapsulation layer and a surface of the first substrate. The shield includes an electromagnetic interference (EMI) shield.

公开(公告)号：WO2017058825A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/054021

申请日：2016-09-27

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Rajneesh ,  KIM, Chin-Kwan ,  SHAH, Milind

IPC: H01L25/065 ,  H01L23/66 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/552 ,  H01L23/66 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19105 ,  H04W4/00 ,  H04W4/80 ,  H01L2924/00012

Abstract: An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package that includes a first electronic package component (e.g., first die) and a second package coupled to the first package. The integrated device includes a first encapsulation layer formed between the first package and the second package. The integrated device includes a second encapsulation layer that at least partially encapsulates the package on package (PoP) device. The integrated device is configured to provide cellular functionality, wireless fidelity functionality and Bluetooth functionality. In some implementations, the first encapsulation layer is separate from the second encapsulation layer. In some implementations, the second encapsulation layer includes the first encapsulation layer. The package on package (PoP) device includes a gap controller located between the first package and the second package.

Abstract translation: 一种集成器件，其包括耦合到印刷电路板（PCB）的印刷电路板（PCB）和封装（PoP）封装。 封装封装（PoP）器件包括包括第一电子封装部件（例如，第一管芯）和耦合到第一封装的第二封装的第一封装。 集成器件包括形成在第一封装和第二封装之间的第一封装层。 集成器件包括至少部分地封装封装（PoP）器件上的封装的第二封装层。 集成设备被配置为提供蜂窝功能，无线保真功能和蓝牙功能。 在一些实现中，第一封装层与第二封装层分开。 在一些实现中，第二封装层包括第一封装层。 封装（PoP）器件包括位于第一封装和第二封装之间的间隙控制器。

公开(公告)号：WO2016049433A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052184

申请日：2015-09-25

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Chin-Kwan ,  KUMAR, Rajneesh ,  ROUHANA, Layal ,  BUOT, Joan Rey V. ,  BCHIR, Omar James

IPC: H01L23/498 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5389 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15333 ,  H01L2924/19041 ,  H01L2924/19106

Abstract: A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity.

Abstract translation: 根据本公开的一些示例的半导体衬底可以包括在衬底的顶表面中具有空腔的衬底，多个腔互连嵌入在腔的底表面下方并延伸到衬底的底表面，并且 多个侧面互连到空腔的任一侧，从基板的顶表面延伸到基板的底表面。 多个侧面互连中的每一个可以包括在与空腔的底部相同的水平平面中的导电停止蚀刻层。

公开(公告)号：WO2016018950A1

公开(公告)日：2016-02-04

申请号：PCT/US2015/042542

申请日：2015-07-28

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Rajneesh ,  JOMAA, Houssam Wafic ,  RAE, David Fraser ,  ROUHANA, Layal ,  BCHIR, Omar James

IPC: H01L23/498

CPC classification number: H01L21/76852 ,  H01L21/4825 ,  H01L21/76879 ,  H01L23/4952 ,  H01L23/49527 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract translation: 一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层，以及第一和第二阻焊层中的开口， 开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。 在一些实施方案中，开口至少部分地填充有导电材料。 导电材料包括焊料和/或互连中的一种。 集成器件包括耦合到导电材料的第一互连。 第一互连是至少焊料和/或互连球之一。 在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。

公开(公告)号：WO2021225880A1

公开(公告)日：2021-11-11

申请号：PCT/US2021/030113

申请日：2021-04-30

Applicant: QUALCOMM INCORPORATED

Inventor： CHATTOPADHYAY, Sayok ,  KUMAR, Rajneesh ,  KULKARNI, Srikanth

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: An integrated circuit (IC) package that is to be incorporated into a computing device may include a metallization structure with circuits and/or other elements such as capacitors or inductors thereon. Pads for input/output (I/O) (or other) purposes may also be present at different locations on the metallization structure. Exemplary aspects of the present disclosure allow mold material to be placed over the circuits and/or other elements in readily-customizable configurations so as to allow placement of the I/O pads in any desired location on the metallization structure. Specifically, before the mold material is applied to the metallization structure, a mask material such as tape may be applied to portions of the metallization structure that contain I/O pads or otherwise have reasons to not have mold material thereon. The mold material is applied, and the mask material is removed, taking unwanted mold material with the mask material.

公开(公告)号：WO2015031280A1

公开(公告)日：2015-03-05

申请号：PCT/US2014/052568

申请日：2014-08-25

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Chin-Kwan ,  KUMAR, Rajneesh ,  BCHIR, Omar James

IPC: H01L23/498

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/3841 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/094 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括第一介电层，第一互连，第一腔和第二互连的衬底。 第一介电层包括第一和第二表面。 第一互连嵌入在第一电介质层中。 第一互连包括第一侧和第二侧。 第一侧被第一介电层包围，其中第二侧的至少一部分与第一介电层不接触。 第一空腔穿过第一介电层的第一表面到第一互连的第二侧，其中第一腔与第一互连重叠。 第二互连包括第三侧和第四侧，其中第三侧耦合到第一介电层的第一表面。

公开(公告)号：WO2022010593A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/034914

申请日：2021-05-28

Applicant: QUALCOMM INCORPORATED

Inventor： HAN, Jeahyeong ,  RAE, David Fraser ,  KUMAR, Rajneesh

IPC: H01L23/552 ,  H01L25/16

Abstract: Packages are configured to include an electromagnetic interference (EMI) shield. According to one example, a package includes a substrate (302), an electrical component (304), and an EMI shield (602). The substrate includes a first surface and a second surface. The electrical component may be coupled to the first side of the substrate. The EMI shield is formed with at least one passive device (312). The at least one passive device is coupled to the first surface of the substrate. The at least one passive device is located laterally to the at least one electrical component, and extends along at least a portion of the electrical component. Other aspects, embodiments, and features are also included.

公开(公告)号：WO2017059141A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/054552

申请日：2016-09-29

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Rajneesh ,  KIM, Chin-Kwan ,  ROGGEMAN, Brian

IPC: H01L25/065

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/01029

Abstract: A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located between the first package and the second package, where the at least one gap controller is configured to provide a minimum gap between the first package and the second package. The first package includes a first electronic package component (e.g., first die). In some implementations, the at least one gap controller is coupled to the first package, but free of coupling with the second package. The at least one gap controller is located on or about a center of the first package. The at least one gap controller may be located between the first electronic package component (e.g., first die) and the second package. The package on package (PoP) device may include an encapsulation layer between the first package and the second package.

Abstract translation: 一种包装（PoP）装置，包括第一包装，耦合到第一包装的第二包装以及位于第一包装和第二包装之间的至少一个间隙控制器，其中至少一个间隙控制器被配置 以提供第一包装和第二包装之间的最小间隙。 第一封装包括第一电子封装部件（例如，第一管芯）。 在一些实施方案中，至少一个间隙控制器耦合到第一封装，但是没有与第二封装的耦合。 所述至少一个间隙控制器位于第一包装的中心或其周围。 至少一个间隙控制器可以位于第一电子封装部件（例如，第一管芯）和第二封装之间。 封装（PoP）设备上的封装可以包括在第一封装和第二封装之间的封装层。

公开(公告)号：WO2014028567A1

公开(公告)日：2014-02-20

申请号：PCT/US2013/054849

申请日：2013-08-14

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Rajneesh ,  BCHIR, Omar, James

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H01L23/14

CPC classification number: H01L24/13 ,  H01L21/4867 ,  H01L23/147 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K3/3468 ,  H05K3/3484 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.

Abstract translation: 迹线装置上的焊料包括在半导体衬底表面上的导电迹线。 导电迹线具有侧壁和接合表面。 跟踪装置上的焊料还包括在导电迹线的至少一端上的钝化层。 跟踪装置上的焊料还包括在侧壁上的预焊料材料和导电迹线的接合表面。