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    Wiring substrate and method of manufacturing the same
    45.
    发明公开
    Wiring substrate and method of manufacturing the same 审中-公开
    Leitersubstrat und Herstellungsverfahrendafür

    公开(公告)号：EP2217045A1

    公开(公告)日：2010-08-11

    申请号：EP10162269.4

    申请日：2007-11-02

    Applicant: IBIDEN CO., LTD.

    Inventor： Yoshikawa, Kazuhiro

    IPC: H05K3/46 ,  H05K1/16

    CPC classification number: H05K1/162 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/113 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09718 ,  H05K2201/10515 ,  H05K2201/10712

    Abstract: The capacitors (350) are formed of the dielectric layer (330) and the first electrode (310) and the second electrode (320) mutually opposing with the dielectric layer (300) being sandwiched therebetween. The laminated capacitor (450) is such that the capacitors (350) are laminated via an adhesive (340). The wiring substrate (900) comprises the first resin insulating layer (200a) with the laminated capacitor (450) built-in, the first via conductors (411) electrically connecting the first electrodes (310) mutually, the second via conductors (412) electrically connecting the second electrodes (320) mutually, the first external terminals (427P) electrically connected to the first via conductors (411), and the second external terminals (427G) electrically connected to the second via conductors (412). The first electrodes (310) and the second electrodes (320) are disposed such that they are mutually offset in the direction of the electrode face.

    Abstract translation: 电容器（350）由夹在其间的电介质层（330）和与电介质层（300）相互相对的第一电极（310）和第二电极（320）形成。 层压电容器（450）使得电容器（350）经由粘合剂（340）层压。 布线基板（900）包括内置层压电容器（450）的第一树脂绝缘层（200a），第一通孔导体（411）相互将第一电极（310）电连接，第二通孔导体（412） 电连接第二电极（320），电连接到第一通孔导体（411）的第一外部端子（427P）和与第二通孔导体（412）电连接的第二外部端子（427G）。 第一电极（310）和第二电极（320）被布置成使得它们在电极面的方向上相互偏移。

    Ceramic capacitor
    47.
    发明公开
    Ceramic capacitor 有权
    Keramikkondensator

    公开(公告)号：EP1761119A1

    公开(公告)日：2007-03-07

    申请号：EP06018353.0

    申请日：2006-09-01

    Applicant: NGK SPARK PLUG CO., LTD

    Inventor： Urashima, Kazuhiro ,  Yuri, Shinji ,  Sato, Manabu ,  Sugimoto, Yasuhiro

    IPC: H05K1/18 ,  H01G2/06 ,  H01G4/12

    CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

    Abstract: A circuit board (10, 10", 10"') comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101', 101'', 101 "', 101'''', 101''''', 101'''''') having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101', 101'', 101 "', 101'''', 101''''', 101'''''') being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

    Abstract translation: 一种电路板（10,10“，10”'），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后电容器（102）的陶瓷电容器（101,101'，101“，101”'，101“，101”'，101“'，101”'，101“ 表面（103）具有其中第一内电极层（141）和第二内电极层（142）交替地层叠有陶瓷介电层（105）并且具有多个电容器功能单元（ 陶瓷电容器101,101'，101“，101”'，101“，101”'，101“'，101”'，101“'，101”'，101“'，101” 在主芯表面（12）和主电容器表面（102）指向相同方向的状态下埋在板芯（11）中; 以及具有其中层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），并具有 半导体集成电路器件安装区域（23,51,52），用于安装在积聚层（31）的表面（39）上具有多个处理器核（24,25）的半导体集成电路器件（21,53,54） ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。

    Wiring board and capacitor to be built into wiring board
    48.
    发明公开
    Wiring board and capacitor to be built into wiring board 有权
    Leiterplatte und Kondensator zum Einbauen in eine Leiterplatte

    公开(公告)号：EP1691590A3

    公开(公告)日：2006-10-18

    申请号：EP06002669.7

    申请日：2006-02-09

    Applicant: NGK Spark Plug Co., Ltd.

    Inventor： Muramatsu, Masaki ,  Yuri, Shinji ,  Urashima, Kazuhiro ,  Yamamoto, Hiroshi ,  Seki, Toshitake ,  Sato, Motohiko

    IPC: H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H01G4/224

    CPC classification number: H01G2/06 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/10 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    Abstract: An intermediate board (200) has a board core composed of a core main body (100m) and a sub-core portion (1). The core main body (100m) is formed into a plate shape by a macromolecular material, and is formed with a sub-core housing portion (100h) which is opened and formed on a first main surface by reducing its thickness. The sub-core portion (1) is formed into a plate shape by ceramic, and is housed in the sub-core housing portion (100h) so that its thicknesswise direction matches with that of the core main body (100m). A first terminal array (5) of the board core (100) is formed in a position where it overlaps the sub-core portion (1) in orthographic projection to a reference surface parallel with a plate surface of the board core (100) . The sub-core portion (1) incorporates a laminated ceramic capacitor where a first electrode conductor layer (54), a ceramic layer (52) and a second electrode conductor layer (57) are laminated periodically in this order. The first electrode conductor layer is conductive with a first side first type terminal (5a) and a second side first type terminal (7a). The ceramic layer is composed of a dielectric layer. The second electrode conductor layer is conductive with a first side second type terminal (5b) and a second side second type terminal (7b). In the sub-core housing portion (100h), an inner edge of the cross section along a plane parallel with a plate surface of the sub-core portion (1) has a quadrate shape, and a radius portion with dimension of not less than 0.1 mm to not more than 2 mm is formed on its corners.

    Abstract translation: 中间板（200）具有由芯主体（100m）和副芯部（1）构成的板芯。 芯主体（100m）通过高分子材料形成为板状，并且形成有通过减小其厚度而在第一主表面上开口形成的子芯收纳部（100h）。 副芯部（1）通过陶瓷形成为板状，并且被容纳在副芯容纳部（100h）中，使其厚度方向与芯主体（100m）的厚度方向一致。 板芯（100）的第一端子阵列（5）形成在与子芯部分（1）重叠的位置，在正交投影中与平行于板芯（100）的板表面的参考表面重叠。 子芯部分（1）包括层叠的陶瓷电容器，其中第一电极导体层（54），陶瓷层（52）和第二电极导体层（57）按顺序周期性地层叠。 第一电极导体层通过第一侧第一型端子（5a）和第二侧第一型端子（7a）导电。 陶瓷层由电介质层构成。 第二电极导体层通过第一侧第二类型端子（5b）和第二侧面第二类型端子（7b）导电。 在子芯收纳部（100h）中，沿着与副芯部（1）的板面平行的平面的横截面的内缘为正方形，尺寸为不小于 0.1mm至不大于2mm的角形成。

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