公开(公告)号：JPH07325761A

公开(公告)日：1995-12-12

申请号：JP2635495

申请日：1995-02-15

Applicant: ADVANCED MICRO DEVICES INC

Inventor： UBE KURANITSUHI

IPC: G06F12/08 ,  G06F12/10

Abstract: PURPOSE: To provide a device and method for decreasing the cache miss penalty of a virtual storage system. CONSTITUTION: This device includes a conversion index buffer 62 operationally connected with a processor core 12 and a memory 16, which receives a virtual address, and generates a correct physical address, theoretical address generating means 42 operationally connected with the conversion index buffer 62 and the memory 16, which generates a theoretical address, and transmits a theoretical address to the memory 16 before the generation of the correct physical address by the conversion index buffer 62, and comparing means 68 operationally connected with the conversion index buffer 62, the memory 16, and the theoretical address generating means 42, which compares the correct physical address with the theoretical address, and transmits the correct physical address to the memory when the correct physical address is not coincident with the theoretical address.

公开(公告)号：JPH07325716A

公开(公告)日：1995-12-12

申请号：JP13401095

申请日：1995-05-31

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUKOTSUTO EI HOWAITO ,  MAIKERU DEII GOTSUDAADO

IPC: G06F9/315 ,  G06F9/38

Abstract: PURPOSE: To provide a method for re-synchronizing the operation of a pipeline processor. CONSTITUTION: A processor 110 updates a fetch program counter in order to fetch an instruction, and simultaneously issues plural instructions in the order. The instructions are inputted to a queue in the reservation station of a functioning unit, and corresponding result entries are assigned to the queue of a reorder buffer 126 in the order of the issue. The execution of the instructions is not operated in the order of the fetch, and the executed results are inputted to the result entries, and collected from that which is present in the head of the queue, and an instruction pointer is updated. The processor 110 detects a resynchronization condition, and when the resynchronization condition is recognized by the result entry corresponding to the instruction, resynchronization is operated. When those entries are collected, the processor 110 flashes the reorder buffer 126 and the station, and re-designates the fetch program counter to the instruction address-designated by the instruction pointer.

公开(公告)号：JPH07321770A

公开(公告)日：1995-12-08

申请号：JP1712095

申请日：1995-02-03

Applicant: ADVANCED MICRO DEVICES INC

Inventor： POORU SHIYUNITSURAIN

IPC: H04B1/38 ,  H04J3/06 ,  H04L7/00 ,  H04M1/725 ,  H04Q7/38

Abstract: PURPOSE: To provide a system and a method for mutually synchronizing the timing of transceiver pairs. CONSTITUTION: A time division multiplex communication system 1 includes plural transceiver pairs CFP1/CPP1, CFP2/CPP2, CFP3/CPP3. Each transceiver pair is driven by a timer included in its inside. Each transceiver pair includes a circuit for synchronizing its own timer with a common frequency signal supplied to the transceiver pair itself. Since the timers of respective transceiver pairs are synchronized with the common frequency signal, the transmission of all transceiver pairs in the system can be mutually synchronized. Since the transmission is synchronized, noises and interference between adjacent transceiver pairs can be reduced.

公开(公告)号：JPH07312546A

公开(公告)日：1995-11-28

申请号：JP4675794

申请日：1994-03-17

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BURATSUDOREE EI SHIYAAPU GIISU

IPC: H03K19/0175 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185

Abstract: PURPOSE: To provide an input buffer circuit for being used by a programmable logical device PLD. CONSTITUTION: An input buffer includes an invertor 200 constituted of a PMOS pull-up transistor 202 in half size of a corresponding NMOS pull-down transistor 204, and TTL compatibility can be obtained. To drive a high capacitance load a cascode transistor 300 is used for controlling the additional pull-up output driver 202 connected with the output of the invertor 200. The cascode 300 turns on the additional pull-up output driver 202, and this is allowed to function for covering the PMOS pull-up transistor 202 during the transition from a low state to a high state of the output. An input buffer includes a switching transistor connected between a VDD power source and the PMOS pull-up transistor 202.

公开(公告)号：JPH07312395A

公开(公告)日：1995-11-28

申请号：JP9839495

申请日：1995-04-24

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIBITSUDO KEI WAI RIU ,  YUU SAN ,  CHII CHIYAN

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To reduce the whole size of a cell without damaging perfectibility of tunnel oxide, by arranging a stacked gate edge on a semiconductor device, forming a spacer on the stacked gate edge, protecting it, and executing self- alignment source etch. CONSTITUTION: A flash EPROM cell 100 contains an oxide region 104 between a first polysilicon layer 102 and a second polysilicon layer 103, and contains a tunnel oxide region 106 between a polysilicon layer 102 and a silicon region 108. A stacked gate edge 502 is formed in the polysilicon region 102. By using spacer 504 formation, the stacked gate edge 502 is protected from being exposed to a self-alignment source process. Thereby safety of tunnel oxide is improved, a uniform source region for spacer formation is generated, and source injection is not given to a part in which silicon is eliminated.

公开(公告)号：JPH07303128A

公开(公告)日：1995-11-14

申请号：JP818095

申请日：1995-01-23

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIRU II GURITSUKU

IPC: H04M1/00 ,  H04M1/253 ,  H04M1/60 ,  H04M1/65 ,  H04M1/738

Abstract: PURPOSE: To provide a telephone controller in which circuits for providing various functions such as a telephone, a digital answering machine, a speakerphone and analog indications are integrated in a single integrated circuit and controlled by a single signal processor. CONSTITUTION: A telephone controller 38 has a control means, including a memory interface for controlling storage in a memory and data retrieval, and the memory interface is linked with a peripheral bus as well. Furthermore, the device 38 converts an audible input signal into digital data and converts the digital data into audible signal outputs through an A/D and D/A converter group with a single digital signal processor 154 as a center. A telephone line interface is connected to the processor 154 and a telephone line 12. A user interface connects a loudspeaker and a microphone to the telephone line interface. The controller 38, the digital signal processor 154, telephone line interface and user interface are all integrated into a common integrated circuit.

公开(公告)号：JPH07295811A

公开(公告)日：1995-11-10

申请号：JP10142795

申请日：1995-04-25

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIERARUDO DEI ZURAASUKI JIYUNI ,  SUKOTSUTO EI HOWAITO ,  MIYURARI ESU CHINNAKONDA ,  DEIBITSUDO ESU KURISUTEII

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

Abstract: PURPOSE: To provide a processor executing operation by an operand with variable size. CONSTITUTION: The processor 10 contains an instruction decoder 18 that includes a means dividing an operand into fields in a variable size operand, a means designating whether or not each field is defined with respect to its operation, and contains a re-order buffer including an operand data storage memory coupled with the decoder 18, a means detecting data dependency to each operand filed independently of other field, buses 30, 31, 32 coupled with the buffer 26 and communicating operand data for a field defined independently of other field, and function units 20, 21, 22, 80 coupled with the buses, executing the operation and generating execution result data.

公开(公告)号：JPH07295695A

公开(公告)日：1995-11-10

申请号：JP8045095

申请日：1995-04-05

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DAGURASU DEII GEFUAATO ,  JIEEMUSU AARU MAKUDONARUDO ,  RITA EMU OBURAIEN

IPC: G06F1/04 ,  G06F1/26 ,  G06F1/32

Abstract: PURPOSE: To provide a computer system including an integrated processor and a method to manage power in the computer system. CONSTITUTION: An integrated processor 102 includes a CPU core 114 connected to an on-chip peripheral device such as a DMA controller, an interrupt controller, and a timer, and a power management message unit 112 connected to the DMA controller, the interrupt controller, and the timer to monitor an internal interrupt signal and a bus request signal of the processor, and the unit monitors a selected activity of the integrated processor. The processor includes the power management unit 104, and the power management unit 104 includes a clock control unit manufactured on an integrated circuit chip apart from the integrated processor and controlling a clock generator.

公开(公告)号：JPH07273796A

公开(公告)日：1995-10-20

申请号：JP1213395

申请日：1995-01-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AREN SOO

IPC: H04L12/56 ,  H04Q11/04

Abstract: PURPOSE: To provide a modular switching architecture for a high-speed packet network. CONSTITUTION: A line interface device LID 40 of the architecture gives frame data in the HDLC form and a clock to a frame relay packet management device FRYPAM 44. The reception FRYPAM 44 performs CRC check, table look-up, and DLCI field conversion to write reception frames having correct FCS fields in a frame buffer and communicates with another FRYPAM 54 to update a transmission queue. A transmission FRYPAM 54 reads out frames from a buffer 46 to send them to a transmission LID coupled to a destination. The transmission LID 50 converts HDLC data to a proper form to transmit frames to the destination terminal. A frame buffer manager 62 assigns the buffer 46 to the FRYPAM 44.

公开(公告)号：JPH07271703A

公开(公告)日：1995-10-20

申请号：JP842395

申请日：1995-01-23

Applicant: ADVANCED MICRO DEVICES INC

Inventor： CHII-SHIUN UU

IPC: G06F13/10 ,  G06F13/12 ,  H03K19/003

Abstract: PURPOSE: To form an integrated Ethernet(R)/SCSI controller to be used on a PCI local bus by integrating the components of SCSI and Ethernet(R) adapter boards on a single chip. CONSTITUTION: This device provided with an SCSI controller and an Ethernet(R) controller is provided with plural VSS3B pin connections and provided with plural connection lines for connecting only one input buffer to one of the VSS3B pins. The device is provided with an analog circuit part 302 and a digital control circuit part 304. The device is further provided with the analog circuit part 302, the digital control circuit part 304, a digital I/O butter part 306 and plural silicon control rectifiers.