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公开(公告)号：US20220262818A1
公开(公告)日：2022-08-18
申请号：US17597926
申请日：2019-07-29
Inventor： Gang Zhang , Zongliang Huo
IPC: H01L27/11582
Abstract: A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively.
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公开(公告)号：US20220254702A1
公开(公告)日：2022-08-11
申请号：US17666790
申请日：2022-02-08
Inventor： Huilong ZHU , Tianchun YE
Abstract: A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.
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53.发明授权公开(公告)号：US11411091B2
公开(公告)日：2022-08-09
申请号：US16954776
申请日：2019-10-30
Inventor： Huaxiang Yin , Tianchun Ye , Qingzhu Zhang , Jiaxin Yao
IPC: H01L29/423 , H01L29/06 , H01L21/8238 , H01L29/66 , H01L29/786 , H01L27/092
Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
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公开(公告)号：US20220246520A1
公开(公告)日：2022-08-04
申请号：US17594753
申请日：2019-05-30
Inventor： Huilong Zhu
IPC: H01L23/522 , H01L23/528
Abstract: An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate.
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公开(公告)号：US11373948B2
公开(公告)日：2022-06-28
申请号：US16969528
申请日：2018-04-13
Inventor： Huilong Zhu
IPC: H01L23/522 , H01L21/768 , H01L23/532
Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided. According to an embodiment, the interconnection structure may comprise: a first interconnection line at a first level, comprising at least a first portion extending along a first direction; a second interconnection line at a second level higher than the first level, comprising at least a second portion extending along a second direction crossing the first direction; a via plug disposed between the first portion of the first interconnection line and the second portion of the second interconnection line, and configured to electrically connect the first interconnection line and the second interconnection line, wherein the via plug comprises a first pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the first portion and a second pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the second portion.
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Patent Agency Ranking
公开(公告)号：US20220172035A1
公开(公告)日：2022-06-02
申请号：US17310203
申请日：2019-01-28
Inventor： Hangbing LV , Xiaoxin XU , Qing LUO , Ming LIU
Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.
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公开(公告)号：US11264461B2
公开(公告)日：2022-03-01
申请号：US16648242
申请日：2019-02-28
IPC: H01L29/16 , C01B32/194 , B32B37/00
Abstract: Disclosed is a graphene electrochemical transfer method assisted by multiple supporting films, comprising: (1) growing graphene on a substrate, and then spin-coating a thin layer of photoresist on a surface of the graphene as a first film; (2) spin-coating n layers of thick, tough, and selectively dissolvable polymer films on the surface of the first film as an top film; (3) dissociating the multi-layer composite film and the graphene from the surface of the substrate by an electrochemical process, and dissolving the thick polymer films which is the top film with a first solvent; (4) after cleaning, transferring the thin first film and the graphene to a target substrate, and finally dissolving the thin first film away with a second solvent to complete the transfer process. This transfer process is fast, stable, and capable of transferring a large-size graphene, which may promote the large-scale application of graphene.
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58.发明申请公开(公告)号：US20210351297A1
公开(公告)日：2021-11-11
申请号：US17281162
申请日：2018-10-31
Inventor： Huilong ZHU
IPC: H01L29/78 , H01L29/423 , H01L29/45 , H01L27/088 , H01L21/8234
Abstract: A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided, and the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.
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公开(公告)号：US11152516B2
公开(公告)日：2021-10-19
申请号：US16586697
申请日：2019-09-27
Inventor： Huilong Zhu
IPC: H01L29/786 , H01L29/66 , H01L29/775 , H01L29/10 , B82Y10/00 , H01L29/06 , H01L29/423 , H01L29/49
Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
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公开(公告)号：US20210295143A1
公开(公告)日：2021-09-23
申请号：US17250569
申请日：2018-08-07
Inventor： Qi Liu , Xumeng Zhang , Ming Liu , Hangbing Lv , Shibing Long
Abstract: A neuron circuit (100), including a memristive element (M1), a trigger element (D1), a feedback element (T1) and an AND circuit (A1). The memristive element (M1) is used to receive an excitation signal. The trigger element (D1) is connected to the memristive element (M1) and is used to receive a clock control signal for the neuron circuit and an output signal of the memristive element (M1). The feedback element (T1) is connected to an output end of the trigger element (D1) and an input end of the memristive element (M1) and is used to control a voltage at the input end of the memristive element (M1). The AND circuit (A1) is used to perform an AND operation on an output signal of the trigger element (D1) and the clock control signal. An output signal of the AND circuit (A1) acts as an output signal of the neuron circuit (100).
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