Method and apparatus for obtaining surface potential

    公开(公告)号:US11366946B2

    公开(公告)日:2022-06-21

    申请号:US16646573

    申请日:2018-08-09

    Abstract: The present disclosure provides a method and an apparatus for obtaining surface potential. The method comprises: obtaining parameter information of multiple target devices, wherein the parameter information includes: size, device structure, material parameter, and carrier mobility of each of the target devices at different temperatures, and the multiple target devices include: devices fabricated by using conventional materials and devices fabricated by using first new materials whose surface potentials have been determined, and the conventional materials include bulk materials and the first new materials include thin film materials; extracting surface potentials based on the size, the device structure, the material parameter and the mobility of each of the target devices under corresponding operating conditions; establishing a surface potential database based on the surface potentials and the parameter information; constructing a surface potential analytical model according to neural network based on the surface potential database; and determining the surface potential of a device fabricated by using a second new material by using the surface potential analytical model.

    Method and apparatus for designing resistive random access memory

    公开(公告)号:US11010530B2

    公开(公告)日:2021-05-18

    申请号:US16647027

    申请日:2018-08-09

    Abstract: The disclosure provides a method and apparatus for designing a resistive random access memory, and the method comprise: receiving a preset first parameter standard of a resistive switching material, searching for and outputting a first resistive switching material based on the first parameter standard, first parameters including: band gap, charge transfer, vacancy, migration barrier, carrier activation energy. Schottky barrier and number of mesophase: establishing a resistive switching material database according to the first resistive switching materials; receiving a second parameter standard for a resistive random access memory device model, and selecting a second resistive switching material from the resistive switching material database according to the second parameter standard, second parameters including: Forming voltage, SET voltage, RESET voltage, erasing and writing speed, power consumption, storage window, stability, durability, on-off ratio, fluctuation of current parameter and storage density of the device model; and designing a resistive random access memory by using the second resistive switching material, corresponding electrode material, and a predetermined storage structure.

    METHOD AND APPARATUS FOR OBTAINING SURFACE POTENTIAL

    公开(公告)号:US20200265176A1

    公开(公告)日:2020-08-20

    申请号:US16646573

    申请日:2018-08-09

    Abstract: The present disclosure provides a method and an apparatus for obtaining surface potential. The method comprises: obtaining parameter information of multiple target devices, wherein the parameter information includes: size, device structure, material parameter, and carrier mobility of each of the target devices at different temperatures, and the multiple target devices include: devices fabricated by using conventional materials and devices fabricated by using first new materials whose surface potentials have been determined, and the conventional materials include bulk materials and the first new materials include thin film materials; extracting surface potentials based on the size, the device structure, the material parameter and the mobility of each of the target devices under corresponding operating conditions; establishing a surface potential database based on the surface potentials and the parameter information; constructing a surface potential analytical model according to neural network based on the surface potential database; and determining the surface potential of a device fabricated by using a second new material by using the surface potential analytical model.

    Preparation method of Cu-based resistive random access memory

    公开(公告)号:US10305035B2

    公开(公告)日:2019-05-28

    申请号:US15744063

    申请日:2016-04-22

    Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: forming a copper wire in a groove through a Damascus copper interconnection process, wherein the copper wire includes a lower copper electrode for growing a storage medium, and the copper wire is arranged above a first capping layer; forming a second capping layer above the copper wire; forming a hole at a position corresponding to the lower copper electrode on the second capping layer, wherein the pore is used for exposing the lower copper electrode; performing composition and a chemical combination treatment on the lower copper electrode to generate a compound barrier layer, wherein the compound barrier layer is a compound formed by the chemical combination of elements Cu, Si and N, or a compound formed by the chemical combination of elements Cu, Ge and N; and depositing a solid electrolyte material and an upper electrode on the compound barrier layer. By means of the above technical solution, the technical problem of higher injection efficiency of Cu ions in the Cu-based resistive random access memory in the prior art is solved, and the fatigue properties of the memory are improved.

    PREPARATION METHOD OF CU-BASED RESISTIVE RANDOM ACCESS MEMORY, AND MEMORY

    公开(公告)号:US20180205015A1

    公开(公告)日:2018-07-19

    申请号:US15744064

    申请日:2016-04-22

    Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: performing composition and a chemical combination treatment on a lower copper electrode (10) to generate a compound buffer layer (40), wherein the compound buffer layer (40) is capable of preventing the oxidation of the lower copper electrode (10); depositing a solid electrolyte material (50) on the compound buffer layer (40); and depositing an upper electrode (60) on the solid electrolyte material (50) to form the memory. In the above technical solution, the compound buffer layer (40) capable of preventing the oxidation of the lower copper electrode (10) is inserted between the lower copper electrode (10) and the solid electrolyte material (50) to efficiently prevent the oxidation of the lower copper electrode (10) in a growth process of the solid electrolyte material (50), such that an electrode interface does not become rough due to the oxidation, thereby solving the technical problem of relatively low reliability and yield of the device resulting from the rough electrode interface of the Cu-based resistive random access memory in the prior art, and thus the reliability and the yield of the device are improved.

    STI STRESS EFFECT MODELING METHOD AND DEVICE OF AN MOS DEVICE
    6.
    发明申请
    STI STRESS EFFECT MODELING METHOD AND DEVICE OF AN MOS DEVICE 审中-公开
    STI应力效应建模方法和MOS器件的设备

    公开(公告)号:US20160259876A1

    公开(公告)日:2016-09-08

    申请号:US14403938

    申请日:2014-04-25

    CPC classification number: G06F17/5068 G06F17/5009 G06F17/5063 G06F2217/80

    Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module. By establishing the function showing that the STI stress effect of the MOS device changes along with the temperature parameters, the influence of the temperature on the STI stress effect of the MOS device can be accurately described, so that the extracted model parameters are more accurate and reliable.

    Abstract translation: 本发明公开了一种MOS器件的STI应力效应建模方法及装置,属于器件参数提取建模技术领域。 该方法包括以下步骤:引入温度参数对MOS器件的STI应力影响的影响,形成MOS器件的STI应力效应随温度参数变化的函数; 在常温下提取MOS器件的Model1型号; 在Model1的基础上,提取STI应力影响常温下MOS器件特性的参数Model2; 并在Model2的基础上,提取功能中MOS器件的拟合参数,以获得最终的模型参数。 该装置包括第一模块,第二模块,第三模块和第四模块。 通过建立显示MOS器件的STI应力效应随温度参数变化的功能,可以准确地描述温度对MOS器件的STI应力影响的影响,从而提取模型参数更准确, 可靠。

    Graphene electrochemical transfer method assisted by multiple supporting films

    公开(公告)号:US11264461B2

    公开(公告)日:2022-03-01

    申请号:US16648242

    申请日:2019-02-28

    Abstract: Disclosed is a graphene electrochemical transfer method assisted by multiple supporting films, comprising: (1) growing graphene on a substrate, and then spin-coating a thin layer of photoresist on a surface of the graphene as a first film; (2) spin-coating n layers of thick, tough, and selectively dissolvable polymer films on the surface of the first film as an top film; (3) dissociating the multi-layer composite film and the graphene from the surface of the substrate by an electrochemical process, and dissolving the thick polymer films which is the top film with a first solvent; (4) after cleaning, transferring the thin first film and the graphene to a target substrate, and finally dissolving the thin first film away with a second solvent to complete the transfer process. This transfer process is fast, stable, and capable of transferring a large-size graphene, which may promote the large-scale application of graphene.

    Self-gating resistive storage device having resistance transition layer in vertical trench in stacked structure of insulating dielectric layers and electrodes

    公开(公告)号:US10720578B2

    公开(公告)日:2020-07-21

    申请号:US16070485

    申请日:2016-04-29

    Abstract: Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer. In the storage device provided by the described technical solution, the gating layer is grown on the lower electrodes by means of self-alignment technique, such that the interlayer leakage channel running through the gating layer is isolated via the insulating dielectric layers; thus leakage between the upper and lower word lines through the gating layer is prevented, solving the technical problem in the prior art of leakage between the upper and lower word lines in a self-gating resistive storage device, and improving the reliability of the device.

    STI stress effect modeling method and device of an MOS device

    公开(公告)号:US10176287B2

    公开(公告)日:2019-01-08

    申请号:US14403938

    申请日:2014-04-25

    Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module. By establishing the function showing that the STI stress effect of the MOS device changes along with the temperature parameters, the influence of the temperature on the STI stress effect of the MOS device can be accurately described, so that the extracted model parameters are more accurate and reliable.

    Preparation method of Cu-based resistive random access memory, and memory

    公开(公告)号:US10700276B2

    公开(公告)日:2020-06-30

    申请号:US15744064

    申请日:2016-04-22

    Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: performing composition and a chemical combination treatment on a lower copper electrode (10) to generate a compound buffer layer (40), wherein the compound buffer layer (40) is capable of preventing the oxidation of the lower copper electrode (10); depositing a solid electrolyte material (50) on the compound buffer layer (40); and depositing an upper electrode (60) on the solid electrolyte material (50) to form the memory. In the above technical solution, the compound buffer layer (40) capable of preventing the oxidation of the lower copper electrode (10) is inserted between the lower copper electrode (10) and the solid electrolyte material (50) to efficiently prevent the oxidation of the lower copper electrode (10) in a growth process of the solid electrolyte material (50), such that an electrode interface does not become rough due to the oxidation, thereby solving the technical problem of relatively low reliability and yield of the device resulting from the rough electrode interface of the Cu-based resistive random access memory in the prior art, and thus the reliability and the yield of the device are improved.

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