公开(公告)号：EP2138961A1

公开(公告)日：2009-12-30

申请号：EP09251325.8

申请日：2009-05-15

Applicant: Renesas Technology Corp.

Inventor： Toriyama, Akihiro ,  Watanabe, Kazuki

IPC: G06K19/07

CPC classification number: G06K19/0723 ,  G06K19/0724

Abstract: A semiconductor integrated circuit and an IC card mounted with the same are provided, in which a signal of any one of at least three kinds of reception signals can be received for a short time. An RF signal from an antenna is supplied in parallel to a first and a second demodulator circuit included in a demodulator circuit. The first demodulator circuit demodulates a first reception signal of a first degree of modulation. The second demodulator circuit demodulates a second reception signal having a first communication start signal (SOF), and a third reception signal having a second communication start signal (Preamble). The demodulated output signals of the first and the second demodulator circuit are supplied to a determination circuit. When the demodulation output by the first demodulator circuit is determined, it is determined that the first reception signal is currently received. When the demodulation output of the second reception signal by the second demodulator circuit is determined, it is determined that the second reception signal is currently received. When the demodulation output of the third reception signal by the second demodulator circuit is determined, it is determined that the third reception signal is currently received.

Abstract translation: 安装有被设置在同一，其中至少3种接收信号中的任何一个的信号可以在短时间内接收的半导体集成电路和IC卡。 从天线的RF信号被供给在平行于第一和包括在解调器电路中的第二解调器电路。 第一解调器电路解调调制的第一程度的第一接收信号。 第二解调器电路解调具有第一通信开始信号（SOF）的第二接收信号，并具有第二通信开始信号（前导）的第三接收信号。 第一和第二解调器电路的解调输出信号被提供给一个判断电路。 当由所述第一解调器电路输出的解调确定性开采，可以确定性开采并目前接收到的第一接收信号。 当由第二解调器电路解调输出的第二接收信号的被确定的开采，其确定性开采并目前接收到的第二接收信号。 当由第二解调器电路解调输出的第三接收信号的被确定的开采，其确定性开采没有当前接收所述第三接收信号。

公开(公告)号：EP2131492A1

公开(公告)日：2009-12-09

申请号：EP07850860.3

申请日：2007-12-19

Applicant: Renesas Technology Corp.

Inventor： OHNISHI, Masami ,  TANAKA, Satoshi ,  TANAKA, Ryouichi

IPC: H03F3/195 ,  H03F3/16 ,  H03F3/60

CPC classification number: H03F3/195 ,  H03F1/0272 ,  H03F1/565 ,  H03F3/245 ,  H03F3/601 ,  H03F3/602 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/108 ,  H03F2200/111 ,  H03F2200/18 ,  H03F2200/207 ,  H03F2200/255 ,  H03F2200/294 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/411 ,  H03F2200/423 ,  H03F2200/451 ,  H03F2200/456 ,  H03F2200/462 ,  H03F2200/465 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/7206 ,  H03F2203/7209

Abstract: An RF amplification device comprises amplification elements Q11 and Q12 which amplify a radio frequency input signal Pin_LB in wireless radio communication, and transmission line transformers TLT11, TLT12, coupled to one of an input electrode and an output electrode of the amplification element. The TLT11, TLT12 comprise a main line Lout arranged between the input and the output, and a sub line Lin1 arranged between an AC ground point and one of the input and the output and coupled to the main line Lout. By applying an operating voltage Vdd different from the ground voltage level GND to the AC ground point, the operating voltage Vdd is supplied to the output electrodes of the amplification elements Q11, Q12 via the sub line Lin from the AC ground point. In realizing a high-performance load circuit in an RF amplification device, it is possible to avoid increase of a module height of an RF module, and at the same time, to avoid increase of an occupied area of a load circuit of a high-frequency amplifier which is formed over a semiconductor chip or a multilayer wiring circuit substrate.

Abstract translation: RF放大装置包括放大无线电通信中的射频输入信号Pin_LB的放大元件Q11和Q12以及耦合到放大元件的输入电极和输出电极之一的传输线变压器TLT11，TLT12。 TLT11，TLT12包括布置在输入和输出之间的主线路由，以及布置在交流地线点与输入和输出之一并耦合到主线路线路上的子线路Lin1。 通过将与接地电压电平GND不同的工作电压Vdd施加到交流接地点，工作电压Vdd经由子线L​​in从AC接地点提供给放大元件Q11，Q12的输出电极。 为了实现RF放大装置中的高性能负载电路，可以避免RF模块的模块高度的增加，同时，为了避免高压负载电路的占用面积的增加， 频率放大器，其形成在半导体芯片或多层布线电路基板上。

公开(公告)号：EP2104031A2

公开(公告)日：2009-09-23

申请号：EP09250320.0

申请日：2009-02-09

Applicant: Renesas Technology Corp.

Inventor： Vuillaume, Camile ,  Okeya, Katsuyuki ,  Yoshino, Masayuki

IPC: G06F7/72

CPC classification number: G06F7/72 ,  G06F2207/7204 ,  H04L9/3033 ,  H04L2209/20 ,  H04L2209/56

Abstract: A technique which contributes to materialization of efficient encryption even with devices such as smartcards restricted in memory resource is provided. The system for generating cryptographic keys includes:
- a calculation unit for reconstructing a large number of small primes,
- a sieving unit for checking the divisibility of an integer by small primes,
- a recoding unit for changing the representation of an integer,
- a primality testing unit.
First, the sieving unit eliminates "bad" candidates by checking their divisibility by small primes reconstructed by the calculation unit. After that, the primality of the remaining candidates is tested using the primality testing unit. The primality testing unit uses the recoding unit to change the representation of prime candidates. The primality testing unit performs a primality test using the represention after change. Thus, the number of operations for the primality test can be decreased without further memory requirements.

Abstract translation: 提供了即使在诸如存储器资源中限制的智能卡之类的设备的情况下有助于实现有效加密的技术。 用于生成加密密钥的系统包括： - 用于重建大量小素数的计算单元， - 用于通过小素数检查整数的可分性的筛选单元， - 用于改变整数表示的记录单元， - 一 原始性检测单位 首先，筛选单位通过由计算单元重构的小素数检查其可分性来消除“不良”候选者。 之后，使用原始性测试单元测试剩余候选人的原始性。 原始测试单元使用记录单元来改变主要候选者的表示。 原始测试单元使用变化后的表示进行原语测试。 因此，可以在没有进一步的存储器要求的情况下减少用于原始性测试的操作的数量。

公开(公告)号：EP1513043B1

公开(公告)日：2009-09-16

申请号：EP04254222.5

申请日：2004-07-14

Applicant: Renesas Technology Corp.

Inventor： Nishizawa, Hirotaka Renesas Technology Corp. ,  Higuchi, Akira Renesas Technology Corp. ,  Osawa, Kenji Renesas Technology Corp. ,  Wada, Tamaki Renesas Technology Corp. ,  Sugiyama, Michiaki Renesas Technology Corp. ,  Osako, Junichiro Renesas Technology Corp.

IPC: G06F1/00 ,  G06K19/077

CPC classification number: G06K19/077 ,  G06K19/07732 ,  H01L23/5388 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

公开(公告)号：EP1693889A3

公开(公告)日：2009-08-12

申请号：EP06447022.2

申请日：2006-02-16

Applicant: IMEC ,  Renesas Technology Corp.

Inventor： Maes, Jan Willem ,  Delabie, Annelies ,  Shimamoto, Yasuhiro ,  Martin Hoyas, Ana

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205

CPC classification number: H01L21/28202 ,  C23C16/0272 ,  C23C16/345 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/31662 ,  H01L21/3185 ,  H01L29/518

Abstract: The present invention relates generally to integrated circuit (IC) fabrication processes.
The present invention relates more particularly to the treatment of surfaces, such as silicon dioxide or silicon oxynitride layers, for the subsequent deposition of a metal, metal oxide, metal nitride and/or metal carbide layer.
The present invention further relates to a high-k gate obtainable by a method of the invention.

公开(公告)号：EP2056509A3

公开(公告)日：2009-06-24

申请号：EP08167467.3

申请日：2008-10-24

Applicant: Renesas Technology Corp.

Inventor： Zhang, Jinyun ,  Peng, Fei

IPC: H04L1/00

CPC classification number: H04L1/002 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0017 ,  H04L5/0046 ,  H04L5/0053 ,  H04L25/0204 ,  H04L25/022

Abstract: A multiple carrier wireless communications system includes a channel predictor, a performance predictor, and a link adapter. The channel predictor is configured to predict channel state information for a next packet based on channel state information for the current packet. The performance predictor includes an uncoded performance predictor configured to predict system performance at an input of a decoder based on a modulation type and the predicted channel state information for the next packet, and a decoder input-output performance mapper configured to determine a required coding rate based on a requested system performance and the predicted system performance at the input of the decoder. The link adapter includes a modulation and coding scheme (MCS) updater configured to identify a MCS based on the required coding rate.

公开(公告)号：EP2053656A2

公开(公告)日：2009-04-29

申请号：EP08253481.9

申请日：2008-10-24

Applicant: Renesas Technology Corp.

Inventor： Okura, Yasutaka c/o Hitachi, Ltd., Int. Prop. Group, ,  Iwasaki, Tomio c/o Hitachi, Ltd., Int. Prop. Group, ,  Terasaki, Takeshi c/o Hitachi, Ltd., Int. Prop. Group,

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01049 ,  H01L2924/01005

Abstract: A technique capable of preventing whiskers which are generated in a plating film formed on the surface of each of leads of a semiconductor device is provided. Particularly, a technique capable of preventing generation of whiskers in a plating film containing tin as a primary material and not containing lead is provided. The plating film formed on the surface of the lead is formed so that a particular plane orientation among plane orientations of tin constituting the plating film is parallel to the surface of the lead. Specifically, the plating film is formed so that the (001) plane of tin is parallel to the surface of the lead. Thus, the coefficient of thermal expansion of tin constituting the plating film can be made to be lower than a coefficient of thermal expansion of the copper constituting the lead.

公开(公告)号：EP2051370A2

公开(公告)日：2009-04-22

申请号：EP08253219.3

申请日：2008-10-02

Applicant: Renesas Technology Corp.

Inventor： Shimamoto, Kenichi ,  Namie, Hisanori

IPC: H03F1/02

CPC classification number: H03F1/0216 ,  H03F3/24 ,  H03F2200/408 ,  H03F2200/451 ,  H03F2200/504 ,  H03F2200/78

Abstract: The RF power amplifier apparatus has an RF power amplifier (RFPA) and a power-supply circuit (Pwr_Cnt). The power-supply circuit controls the level of a source voltage (V LDO ) supplied to the RF power amplifier in response to the level of a power-control signal (Vapc). A sensing resistance (Rsen) produces a sense signal (Vsen) corresponding to a source current (I LDO ) with respect to a source voltage. A current-control unit (Cmp1,Cmp2,FF1,NAND3 and Qp4) controls the source current (I LDO ) in response to the sense signal (Vsen). When Vsen coincides with an allowable sense signal level (Vsh) corresponding to a source current allowable level I LDO (Max), the current-control unit controls the source current (I LDO ) to a limit current smaller than the allowable level I LDO (Max). Preferably, the limit current is a shutdown current when a shutdown switch is in OFF state. Thus, the drain of the battery of a mobile-phone terminal can be reduced even when an impedance mismatch condition lasts for a long time.

Abstract translation: 所述RF功率放大装置具有RF功率（RFPA）和电源供给电路（Pwr_Cnt）的放大器。 电源电路控制响应于功率控制信号（VAPC）的电平供给到RF功率放大器的电源电压（V LDO）的电平。 感测电阻（器Rsen）产生相对于源极电压对应于源电流（I LDO）的感测信号（Vsen要）。 一种电流控制单元（CMP 1，器Cmp2，FF1，NAND3和QP4）控制，响应于所述感测信号（Vsen要）的源极电流（I LDO）。 当Vsen要与允许检测信号电平一致（VSH）对应于源电流的允许电平I LDO（最大值）时，电流控制单元控制所述源极电流（I LDO）的限制电流比容许水平I LDO较小（ 最大）。 优选地，限制电流为关断电流关断时的开关处于OFF状态。 因此，移动电话终端的电池的漏极可以即使当阻抗失配状态持续了很长的时间被减少。

公开(公告)号：EP2048583A2

公开(公告)日：2009-04-15

申请号：EP08252686.4

申请日：2008-08-13

Applicant: Renesas Technology Corp.

Inventor： Nonomura, Itaru

IPC: G06F13/42

CPC classification number: G06F13/4045 ,  Y02D10/14 ,  Y02D10/151

Abstract: A data processing system enabling an outstanding-based variable flow control is provided. The data processing system includes a first semiconductor integrated circuit possessing an initiator and a second semiconductor integrated circuit possessing a target. The initiator transmits a request packet to the target, the target transmits a response packet to the initiator, and split transaction interface is practiced. The initiator includes an outstanding number counting circuit for counting an outstanding number defined by the difference in number between the request packets transmitted and the response packets received. The request packet transmission number is controlled so that the count value of the outstanding number counting circuit may not exceed the outstanding number to which the target can respond. The outstanding number is dynamically changeable to a suitable number so that the maximum latency from the issue of the request packet to the reception of the response packet is suppressed.

Abstract translation: 提供了能够实现基于突出的可变流量控制的数据处理系统。 数据处理系统包括具有起始器的第一半导体集成电路和具有目标的第二半导体集成电路。 发起者向目标发送请求分组，目标向发起者发送响应分组，实现分组事务接口。 启动器包括一个未完成的号码计数电路，用于对由发送的请求分组和接收到的响应分组之间的数量差异定义的未完成号码进行计数。 控制请求分组发送次数，使得未完成号码计数电路的计数值不能超过目标可以响应的未决号码。 未完成的号码可以动态地改变为合适的号码，从而抑制从发出请求分组到接收响应分组的最大等待时间。

公开(公告)号：EP2023393A1

公开(公告)日：2009-02-11

申请号：EP06756849.3

申请日：2006-05-31

Applicant: Renesas Technology Corp.

Inventor： TAKAURA, Norikatsu ,  MATSUI, Yuichi ,  TERAO, Motoyasu ,  FUJISAKI, Yoshihisa ,  MATSUZAKI, Nozomu ,  KUROTSUCHI, Kenzo ,  MORIKAWA, Takahiro

IPC: H01L27/105 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge-Sb-Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge-Sb-Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

Abstract translation: 在其中嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽制成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层 导入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过在记录层（52）和插塞（43）之间插入绝缘膜（51），可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。