公开(公告)号：US20160163595A1

公开(公告)日：2016-06-09

申请号：US14888674

申请日：2014-04-30

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Heui Gyun AHN ,  Sang Wook AHN ,  Yong Woon LEE ,  Huy Chan JUNG ,  Do Young LEE

IPC: H01L21/768 ,  H01L21/683 ,  H01L21/306

CPC classification number: H01L21/76898 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/7684 ,  H01L2221/68327 ,  H01L2221/68359

Abstract: A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.

Abstract translation: 用于制造通孔硅通孔（TSV）的方法采用传统的沟槽绝缘工艺来容易地制造通孔硅通孔（TSV），从而实现通孔硅通孔（TSV）和通孔硅通孔（TSV）之间的有效电绝缘 硅。

公开(公告)号：US09337228B2

公开(公告)日：2016-05-10

申请号：US14468843

申请日：2014-08-26

Applicant: SiliconFile Technologies Inc.

Inventor： Seung Hoon Sa ,  Young Ha Lee

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14609 ,  H01L27/14634 ,  H01L27/1464

Abstract: An image sensor cell is divided into two chips, and a capacitor for noise reduction is formed in a bottom wafer in correspondence with a unit pixel of a top wafer in a stack chip package image sensor having a coupling structure of the two chips, so that noise characteristics of the image sensor are improved. A stack chip package image sensor includes: a first semiconductor chip that includes a photodiode, a transmission transistor, and a first conductive pad and outputs image charge, which is output from the photodiode, through the first conductive pad; and a second semiconductor chip that includes a drive transistor, a selection transistor, a reset transistor, and a second conductive pad and supplies a corresponding pixel with an output voltage corresponding to the image charge received from the first semiconductor chip through the second conductive pad. The second semiconductor chip includes a capacitor for noise reduction.

Abstract translation: 图像传感器单元被分成两个芯片，并且在具有两个芯片的耦合结构的堆叠芯片封装图像传感器中的顶部晶片的单位像素的底部晶片中形成用于降低噪声的电容器，使得 提高了图像传感器的噪声特性。 堆叠芯片封装图像传感器包括：第一半导体芯片，其包括光电二极管，透射晶体管和第一导电焊盘，并且通过第一导电焊盘输出从光电二极管输出的图像电荷; 以及包括驱动晶体管，选择晶体管，复位晶体管和第二导电焊盘的第二半导体芯片，并且通过第二导电焊盘向相应像素提供与从第一半导体芯片接收的图像电荷相对应的输出电压。 第二半导体芯片包括用于降噪的电容器。

公开(公告)号：US20150155323A1

公开(公告)日：2015-06-04

申请号：US14399735

申请日：2012-05-10

Applicant: SiliconFile Technologies Inc.

Inventor： Heui Gyun Ahn ,  Jun Ho Won

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14616 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present invention relates to a chip-stacked image sensor and to a method for manufacturing the same. More particularly, the present invention relates to a chip-stacked image sensor having a heterogeneous junction structure and to a method for manufacturing the same, in which a first semiconductor chip and a second semiconductor chip are manufactured using substrate materials suitable for the characteristics of sensors formed on each semiconductor substrate, and the semiconductor chips are stacked to form an image sensor. According to the chip-stacked image sensor having a heterogeneous junction structure and the method for manufacturing the same, the material for a first semiconductor substrate used in a first semiconductor chip and the material for a second semiconductor substrate used in a second semiconductor chip are different from each other, thus enabling characteristics of sensors formed on each semiconductor chip to be properly exhibited.

Abstract translation: 芯片堆叠式图像传感器及其制造方法技术领域本发明涉及芯片堆叠式图像传感器及其制造方法。 更具体地，本发明涉及具有异质结结构的芯片堆叠图像传感器及其制造方法，其中使用适合于传感器特性的基板材料制造第一半导体芯片和第二半导体芯片 形成在每个半导体衬底上，并且半导体芯片被堆叠以形成图像传感器。 根据具有异质结结构的芯片堆叠图像传感器及其制造方法，用于第一半导体芯片的第一半导体衬底的材料和用于第二半导体芯片中的第二半导体衬底的材料是不同的 从而能够适当地显示形成在各半导体芯片上的传感器的特性。

公开(公告)号：US08993411B2

公开(公告)日：2015-03-31

申请号：US13775178

申请日：2013-02-23

Applicant: Siliconfile Technologies Inc.

Inventor： Heui-Gyun Ahn ,  Se-Jung Oh ,  In-Gyun Jeon ,  Jun-Ho Won

IPC: H01L21/46 ,  H01L23/00 ,  H01L21/683 ,  H01L23/48 ,  H01L27/146

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/05 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/68372 ,  H01L2224/05093 ,  H01L2924/01046 ,  H01L2924/01078

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.

Abstract translation: 公开了一种用于在具有三维堆叠结构的晶片中形成焊盘的方法。 该方法包括将包括Si衬底和处理晶片的器件晶片接合，使Si衬底的背面变薄，在Si衬底的减薄的背侧上沉积抗反射层，在其上沉积背面电介质层 防反射层，在背面电介质层中形成用于焊盘的空间，并且形成穿过形成在Si衬底上的超级触点的背面电介质层和抗反射层和接触背面的通孔，填充 通孔中的一种或多种金属和用于垫的限定空间，以及通过CMP（化学机械抛光）工艺通过平坦化除去填充在垫的空间中的剩余量的金属。

公开(公告)号：US20150053846A1

公开(公告)日：2015-02-26

申请号：US14466258

申请日：2014-08-22

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Kyung Su BYUN

IPC: H01L27/146 ,  H04N13/02 ,  H04N5/232

CPC classification number: H01L27/14629 ,  H01L27/14634 ,  H01L27/14647 ,  H01L27/1469

Abstract: Disclosed is an image sensor with a 3D stack structure, in which pixels of a top plate are realized as image pixels and pixels of a bottom plate are realized as pixels for realizing a phase difference AF, so that the phase difference AF is realized without loss of resolution. In the image sensor with a 3D stack structure, a problem of the reduction of resolution, which is a disadvantage of an existing imaging surface phase difference AF device, is solved, so that a fast phase difference AF is realized while maintaining high resolution without a separate phase difference AF module.

Abstract translation: 公开了一种具有3D堆叠结构的图像传感器，其中顶板的像素被实现为图像像素，并且底板的像素被实现为用于实现相位差AF的像素，使得相位差AF被实现而没有损失 的决议。 在具有3D堆叠结构的图像传感器中，解决了现有成像面相位差AF装置的缺点的分辨率降低的问题，从而实现快速相位差AF，同时保持高分辨率而没有 单独的相位差AF模块。

公开(公告)号：US20140327061A1

公开(公告)日：2014-11-06

申请号：US14359264

申请日：2012-11-08

Applicant: SiliconFile Technologies Inc.

Inventor： Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14647 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14641

Abstract: The present invention relates to a substrate stacked image sensor having a dual detection function, in which when first to fourth photodiodes are formed in a first substrate, a fifth photodiode is formed in a second substrate, and the substrates are stacked and combined with each other, the first to fourth photodiodes and the fifth photodiode are combined with each other to obtain a complete photodiode as an element of one pixel, and signals individually detected in each photodiode are selectively read or added to be read according to necessity. To this end, the first to fourth photodiodes are formed in the first substrate, the fifth photodiode is formed in the second substrate, the first to fourth photodiodes and the fifth photodiode make electrical contact with each other, and pixel array sizes of the first substrate and the second substrate are allowed to be different from each other, so that sensor resolution of the first substrate and sensor resolution of the second substrate are different from each other.

Abstract translation: 本发明涉及具有双重检测功能的基板层叠图像传感器，其中当在第一基板中形成第一至第四光电二极管时，在第二基板中形成第五光电二极管，并且将基板彼此堆叠并组合 ，第一至第四光电二极管和第五光电二极管彼此组合以获得作为一个像素的元件的完整光电二极管，并且根据需要选择性地读取或添加在每个光电二极管中单独检测的信号以进行读取。 为此，第一至第四光电二极管形成在第一衬底中，第五光电二极管形成在第二衬底中，第一至第四光电二极管和第五光电二极管彼此电接触，第一衬底的像素阵列尺寸 并且第二基板被允许彼此不同，使得第一基板的传感器分辨率和第二基板的传感器分辨率彼此不同。

公开(公告)号：US20140293099A1

公开(公告)日：2014-10-02

申请号：US14306965

申请日：2014-06-17

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Do-Young LEE

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H04N9/045 ,  H04N2209/045 ,  H04N2209/047

Abstract: Provided is a pixel array having a wide dynamic range, good color reproduction, and good resolution and an image sensor using the pixel array. The pixel array includes a plurality of first type photodiodes, a plurality of second type photodiodes, and a plurality of image signal conversion circuits. A plurality of the second type photodiodes are disposed between the first type photodiodes which are two-dimensionally arrayed. A plurality of the image signal conversion circuits are disposed between the first type photodiodes and the second type photodiodes to process image signals detected by the first type photodiodes and the second type photodiodes. An area of the first type photodiodes is wider than an area of the second type photodiodes.

Abstract translation: 提供了具有宽的动态范围，良好的色彩再现和良好的分辨率的像素阵列以及使用像素阵列的图像传感器。 像素阵列包括多个第一类型光电二极管，多个第二类型光电二极管和多个图像信号转换电路。 多个第二类型光电二极管设置在二维排列的第一类型光电二极管之间。 多个图像信号转换电路设置在第一类型光电二极管和第二类型光电二极管之间，以处理由第一类型光电二极管和第二类型光电二极管检测的图像信号。 第一类型光电二极管的区域比第二类型光电二极管的区域宽。

公开(公告)号：US09875529B2

公开(公告)日：2018-01-23

申请号：US15056472

申请日：2016-02-29

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Bo Ra Lee ,  Du Su Shin

IPC: G06T5/20 ,  G06T5/00

CPC classification number: G06T5/002 ,  G06T5/20 ,  G06T2207/20032

Abstract: A device for removing a noise on an image using a cross-kernel type median filter includes a target pixel determination unit configured to determine whether a target pixel is a noise or not; a peripheral pixel determination unit configured to determine degrees of the noise on a peripheral pixel information of a peripheral pixel of the target pixel; and a noise removing unit configured to remove the noise of the target pixel and corrects the image by applying a cross-kernel type median filter based on the peripheral pixel information.

公开(公告)号：US20170237911A1

公开(公告)日：2017-08-17

申请号：US15029572

申请日：2014-11-06

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Jun-Ho WON

IPC: H04N5/33 ,  H04N9/64 ,  H04N5/357 ,  H01L27/146

CPC classification number: H04N5/33 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14645 ,  H01L27/1465 ,  H04N5/332 ,  H04N5/357 ,  H04N5/359 ,  H04N5/37457 ,  H04N5/379 ,  H04N9/045 ,  H04N9/646

Abstract: The present invention relates to an image sensor sensor having improved spectral characteristics, and improves a color characteristic and sensitivity of an image sensor by implementing an image sensor sensor using a stacked substrate structure having photodiodes formed on each of two substrates, and generating a color signal having improved spectral characteristics based on an electrical signal outputted from each of the photodiodes formed on two substrates.

公开(公告)号：US20160321196A1

公开(公告)日：2016-11-03

申请号：US15108537

申请日：2014-11-27

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Seong Jun PARK ,  Huy Chan JUNG ,  Sang Wook AHN

IPC: G06F13/16

CPC classification number: G06F13/1605 ,  G06F13/1689

Abstract: The present invention relates to a technology enabling a normal access by controlling a read access through an arbiter in a circuit for controlling an access to memory to which clock signals are input through two ports, respectively for a read access to a single port memory. The present invention includes an arbiter that generates an internal clock signal through a state transition among a first state for generating a first clock signal, a second state for generating a second clock signal, a standby state and a neutral state when generating the internal clock signal for reading data from the memory on the basis of the first clock signal and the second clock signal, and a read end signal that is supplied from the memory.

Abstract translation: 本发明涉及通过控制通过用于控制对通过两个端口输入时钟信号的存储器的访问的电路中的仲裁器的读取访问来分别用于对单个端口存储器的读取访问的技术。 本发明包括一个仲裁器，它通过产生第一时钟信号的第一状态，产生第二时钟信号的第二状态，产生内部时钟信号时的待机状态和空档状态之间的状态转换产生内部时钟信号 用于基于第一时钟信号和第二时钟信号从存储器读取数据，以及从存储器提供的读取结束信号。