公开(公告)号：JP2014042021A

公开(公告)日：2014-03-06

申请号：JP2013164297

申请日：2013-08-07

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc.

Inventor： LIU QING ,  PRASANNA KHARE ,  NICOLAS LOUBET

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a multi-fin FINFET device which is reliable and easy to manufacture, and a method for manufacturing the same.SOLUTION: A multi-fin FINFET device may have a substrate and a plurality of semiconductor fins extending upward from the substrate and isolated along the substrate. Each of the semiconductor fins may have first and second ends on both sides and an intermediate part therebetween, and an outermost fin among the plurality of semiconductor fins may have an epitaxial growth barrier on its outer surface. The FINFET further may have at least one gate above the intermediate part of the semiconductor fin, a plurality of swell type epitaxial semiconductor source regions adjacent to a first end thereof and between semiconductor fins, and a plurality of swell type epitaxial semiconductor drain regions adjacent to a second end thereof and between semiconductor fins.

Abstract translation: 要解决的问题：提供一种可靠且易于制造的多鳍FINFET器件及其制造方法。解决方案：多鳍FINFET器件可以具有衬底和从 衬底并沿衬底分离。 每个半导体翅片可以在其两侧具有第一和第二端以及它们之间的中间部分，并且多个半导体翅片中的最外面的翅片在其外表面上可以具有外延生长阻挡层。 FINFET还可以在半导体鳍片的中间部分上方具有至少一个栅极，与其第一端相邻并且在半导体鳍片之间的多个隆起型外延半导体源极区域以及与其相邻的多个隆起型外延半导体漏极区域 其第二端和半导体鳍片之间。

公开(公告)号：JP2014042019A

公开(公告)日：2014-03-06

申请号：JP2013164024

申请日：2013-08-07

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc.

Inventor： LIU QING ,  PRASANNA KHARE ,  NICOLAS LOUBET

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/76816 ,  H01L21/823425 ,  H01L21/823864 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device whose contact resistance is reduced, and a method thereof.SOLUTION: A semiconductor device includes a semiconductor substrate comprising a channel region, a gate component above the channel region, and source and drain regions on both sides of the gate component. Contacts are respectively provided on the source and drain regions. At least one of the source and drain regions is provided with a gradient type upper contact surface with the respective contacts. The gradient type upper contact surface has an area at least 50% larger than that of a corresponding flat contact surface.

Abstract translation: 要解决的问题：提供一种接触电阻降低的半导体器件及其方法。解决方案：一种半导体器件包括半导体衬底，该半导体衬底包括沟道区，沟道区上方的栅极元件以及两者上的源极和漏极区 门组件的两侧。 触点分别设置在源极和漏极区域上。 源极和漏极区域中的至少一个具有与各个触点的梯度型上接触表面。 梯度型上接触面的面积比对应的平坦接触表面的面积至少大50％。

公开(公告)号：JPH11164824A

公开(公告)日：1999-06-22

申请号：JP25838298

申请日：1998-09-11

Applicant: ST MICROELECTRON INC

Inventor： KALNITSKY ALEXANDER ,  KRAMER ALAN

IPC: G01B7/28 ,  A61B5/117 ,  G06F3/033 ,  G06F3/044 ,  G06K9/00 ,  G06T1/00

Abstract: PROBLEM TO BE SOLVED: To obtain a finger mark detecting device capable of avoiding influence of static electricity charged on the finger tip, by setting a number of metal passages in a dielectric layer and spatially surrounding first and second capacitor plates in the dielectric layer. SOLUTION: An array for finger mark pattern detection comprises an IC device 1 with a sensor array 3 of multi-row/column, and the array 3 has a number of solid state capacitor type sensor cells 2. The individual cell 2 of the sensor array 3 is positioned at the cross point of a row in the horizontal direction and a column in the vertical direction to make the cell possible to address and is sequentially checked by networks 6, 5 in horizontal and vertical directions according to a prescribed self-scanning pattern. Each cell 2 has constitution that two XY flat metal capacitor plates 23, 24 not grounded and metal grids 40 electrically separated from the capacitor plates 23, 24 and electrically grounded are buried in the dielectric layer 25.

公开(公告)号：JPH11164001A

公开(公告)日：1999-06-18

申请号：JP27413798

申请日：1998-09-29

Applicant: ST MICROELECTRON INC

Inventor： COLAVIN OSVALDO

IPC: H04M1/274 ,  H04M1/2755 ,  H04M11/00

Abstract: PROBLEM TO BE SOLVED: To provide a telephone system and method with integrated telephone bar code reader for performing dial operation and information transmission through a telephone circuit network. SOLUTION: A telephone system 20 has a controller ROM code for interpreting bar code scanner and bar code reader outputs and generating an appropriate dual tone multifrequency(DTMF) pulse and a means for triggering execution. The user of this telephone system turns the bar code scanner toward a bar code, activates the trigger device of button or toggle, for example, and triggers the execution. Next, a bar code reader 24 scans bar code information, a bar code reader input is interpreted, and the appropriate DTMF pulse is transmitted through the telephone circuit network.

公开(公告)号：JPH1187529A

公开(公告)日：1999-03-30

申请号：JP18261598

申请日：1998-06-29

Applicant: ST MICROELECTRON INC

Inventor： NGUYEN LOI N

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To form a contact having high aspect ratio. SOLUTION: Nitride spacers 28, 30 are formed along a gate electrode 24 for partitioning a lightly doped drain(LDD) region. Further, in the case of forming a nitride cap layer 18 on a gate electrode and forming a contact opening 20 via an interlayer oxide dielectric film, the cap and sidewall spacers are protected so that the electrode 24 is not damaged or short-circuited. Then, a plug 42 made of heavily doped polysilicon is formed in the opening, and a board 10 existing at a lower side, namely, a contact is formed. A metallization is formed on the polysilicon plug 42 in a normal form.

公开(公告)号：JPH1174378A

公开(公告)日：1999-03-16

申请号：JP17768898

申请日：1998-06-24

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU ,  BRYANT FRANK RANDOLPH

IPC: H01L21/8244 ,  H01L27/11 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM(static random access memory) cell and the manufacture for reducing a memory area without degrading performance. SOLUTION: Two P type bulk silicon pull-down transistors 18 and 22 formed by two polysilicon layers, two N type active gate type pull-up TFTs(thin film transistors) 16 and 20, and two path gates 28 and 30, are mutually connected by four shared contacts 24 and 26. One polysilicon 1 of the polysilicon layers is turned to salicide and is provided with a gate electrode for the P type pull- down transistors 18 and 22, and the other polysilicon 2 is provided with a desired polysilicon 2 stringer disposed along the side part edge of the side part of the polysilicon 1 gate electrode and forms the channel area of the pull-up TFTs 16 and 20.

公开(公告)号：JPH1166505A

公开(公告)日：1999-03-09

申请号：JP16380798

申请日：1998-06-11

Applicant: ST MICROELECTRON INC

Inventor： PATTI GUISEPPE

IPC: G11B5/09 ,  G01R33/09 ,  G11B5/02 ,  G11B5/39 ,  H03F1/26

Abstract: PROBLEM TO BE SOLVED: To supply a small amount of current from a high load resistance to obtain a large gain at a first stage thereby reducing a noise by supplying a constant amount of current from a pair of current sources to a first stage of a preamplifier to obtain a current sufficient for reducing a bias current applied via an MR readout head so as to disappear. SOLUTION: A preamplifier 50 supplies from first and second current sources 80 and 82 a constant amount of current which is sufficient for reducing a bias current to be applied via an MR readout head 60 (RH) so as to disappear. As a result, a relatively small amount of current is supplied from a load resistance 56 thereby allowing a resistance value RL of the load resistance 56 to increase. Accordingly, it is possible to obtain a relatively large gain at a first amplifying stage 52 composed of the load resistance 56, an NPN bipolar transistor 58 and the MR readout head 60. Thus, noise contribution of the load resistance 56 is reduced and noise contribution of a second amplifying stage 54 can also be significantly reduced.

公开(公告)号：JPH1145980A

公开(公告)日：1999-02-16

申请号：JP5978898

申请日：1998-03-11

Applicant: ST MICROELECTRON INC

Inventor： BRADY JAMES

IPC: H01L27/04 ,  G06F1/18 ,  H01L21/822 ,  H03B1/04 ,  H03B5/32 ,  H03H7/01

Abstract: PROBLEM TO BE SOLVED: To provide a technique for reducing noise in a small-current low frequency circuit provided on a large current high frequency integrated circuit chip. SOLUTION: Components which are affected by noise in a small-current low frequency circuit 62 are positioned outside an integrated circuit chip 52 as an off-chip array. An exclusive power reference line VSS( REF) is wired as extended from a power bus in the integrated circuit chip via a tap. The reference line VSS( REF) is led out from an inner power bus of an on-chip via a tap at a physical position adjacent to the small current low frequency circuit and then routed to the off-chip. Components which are affected by noise are provided between the small current low frequency circuit 62 and the reference line VSS( REF) . In this case, a noise difference between power supplied to the small current low-frequency circuit of the off-chip and power supplied to the noise- affected components can be minimized.

公开(公告)号：JPH10334656A

公开(公告)日：1998-12-18

申请号：JP13359598

申请日：1998-05-15

Applicant: ST MICROELECTRON INC

Inventor： ARTIERE ALAIN

IPC: G11C11/412 ,  G11C11/401 ,  G11C11/402 ,  G11C11/403 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To implement in parallel many refresh operations in single cycle and reduce bandwidth for refresh operation by setting individual memory cell access and memory transistors in such a ratio of the modes to refresh the memory cell information with activation of the related word line. SOLUTION: An individual dynamic memory cell 102 of a dynamic memory cell 100 couples the drains of a pair of cross-connected N-channel MOS transistors 104, 106 to the bit lines 114, 116 via the N-channel access transistors 108, 110 and then connects the gates of transistors 1089, 110 to the word line 112. The refresh operation of memory cell 100 is performed by enabling the gate of transistor 108 and then activating the word line 112. Thereby, the memory cell 102 can be refreshed simultaneously using the multi-word line activating circuit 126.

公开(公告)号：JPH10304652A

公开(公告)日：1998-11-13

申请号：JP35363997

申请日：1997-12-22

Applicant: ST MICROELECTRON INC

Inventor： HOPKINS THOMAS L

IPC: H02M3/00 ,  H03K5/13 ,  H03K7/08

Abstract: PROBLEM TO BE SOLVED: To provide an improved synchronous circuit for switching regulator by generating programmable pulse modulation output, so as to be synchronized in frequency and have duty cycle and phase shift which are selectable by a user and whose output is independent. SOLUTION: A circuit 11 involves four output modules 21a to 21d for respective pulse width modulation output. The respective output modules 21a to 21d generate the pulse width modulation outputs PWM1 to PWM4 which can conduct programming, so that it is high or low based on the values held by respective comparison registers 31, 39. Therefore, each of the output modules 21a to 21d can be programmed so as to generate independent pulse width modulation outputs PWM1 to PWM4 synchronized with the frequency of 4-bit counter 17 by duty cycle and phase shift which are selectable independently. In this case, the output module 21a is structurally identical to the output modules 21b to 21c in its structure.