公开(公告)号：JP2001119251A

公开(公告)日：2001-04-27

申请号：JP2000261125

申请日：2000-08-30

Applicant: ST MICROELECTRONICS SA

Inventor： BELOT DIDIER

IPC: H03F1/22 ,  H03F3/191 ,  H03F3/45 ,  H04B1/18 ,  H04B1/40

Abstract: PROBLEM TO BE SOLVED: To provide a new radio frequency signal receiving head which is assigned to a dual band system by using only a signal low noise amplifier. SOLUTION: This amplifier circuit includes at least one 1st input amplifier T1, at least one 2nd amplifier T3 cascaded with the 1st amplifier and at least one invalid impedance circuit which includes two impedances Z1 and Z2 respectively showing a maximum value to 1st and 2nd frequencies f1 and f2 to form a dual band amplifier circuit and is serially attached to the 2nd amplifier. The impedances Z1 and Z2 are serially connected and made to be a size so as to respectively show the maximum value and high acutance by one of the two operation frequencies f1 and f2.

公开(公告)号：JP2001086044A

公开(公告)日：2001-03-30

申请号：JP2000218500

申请日：2000-07-19

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  ENGUENT JEAN-PIERRE

IPC: G06K7/08 ,  G06K19/07 ,  H04B1/59 ,  H04B5/00

Abstract: PROBLEM TO BE SOLVED: To permit operation only in an extreme proximity to prevent the surreptitious use due to interception by allowing a resonance circuit to have a specific characteristic that an electromagnetic coupling coefficient is suddenly reduced when the distance exceeds a prescribed value between a write/read terminal and an electromagnetic transponder. SOLUTION: The voltage that is induced by a transponder 10 is maximized with an optimum coupling coefficient set between a serial resonance circuit including a resistor R1, an inductance L1 and a capacitor C1 of a terminal 1 and a parallel oscillation circuit including an inductance L2 and a capacitor C2 of the transponder 10 and then reduced sharply on both sides of the transponder 10. Then the optimum coupling coefficient is expressed by a square root of R1L2/R2L1 with equivalent resistor R2 of the transponder 10, and each parts value of every oscillation circuit is set to secure the maximum voltage with a prescribed distance. In other words, the capacitor C2 that can obtain a prescribed frequency with a distance of 1 cm is reduced as much as possible and then the value of inductances L2 and L1 and capacitor C1 are successively set.

公开(公告)号：JP2001023998A

公开(公告)日：2001-01-26

申请号：JP2000156466

申请日：2000-05-26

Applicant: ST MICROELECTRONICS SA

Inventor： GRIS YVON

IPC: H01L29/417 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/73

Abstract: PROBLEM TO BE SOLVED: To obtain a manufacturing method of a bipolar transistor which forms a self-aligned type base-emitter junction. SOLUTION: On a p-type substrate, an n-type region 2 and an n-type region 3, the active region of which is determined by an insulator 4. The regions are covered with an insulation layer 5 and a mask, and the insulation layer 5 is etched to make an opening, then heavily-doped n-type impurity is implanted to the bottom of the region 3 to form a collector bottom 7. On the exposed layer 3, a p-type silicon base layer 10 and spacers 8-1 and 8-2 are deposited. An oxidized silicon insulating layer is deposited, and a spacer 11 is formed through anisotropic etching, while an n-type polysilicon emitter layer 12 is formed, then upper top face and that of the spacer 11 are planarized. A base electrode 16-1 and an emitter electrode 16-2 are formed through silicified contact surfaces 13 and 14.

公开(公告)号：JP2001007730A

公开(公告)日：2001-01-12

申请号：JP2000103473

申请日：2000-04-05

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  BARDOUILLET MICHEL ,  ENGUENT JEAN-PIERRE

IPC: G06K17/00 ,  G01S13/75 ,  G01S13/76 ,  G01S13/79 ,  G06K7/00 ,  G06K19/07 ,  H02J17/00 ,  H04B1/59 ,  H04L27/02

Abstract: PROBLEM TO BE SOLVED: To realize distance detection between a transponder and a terminal, which is executed on a terminal side and which does not require transmission from the transponder for the evaluation of the distance, by measuring a variable decided by a load formed on the oscillation circuit of the terminal through the means of the transponder. SOLUTION: A terminal 1' is located between the output terminal 2p of an amplifier, namely, an antenna coupler 3 and a prescribed terminal 2m in a reference potential, and it comprises an oscillation circuit formed of a capacitive part 24 and an inductance connected to a resistor R1 in series, namely an antenna L1. Voltage between the connection point 30 of the resistor R1 in the oscillation circuit and the inductance L1 and a ground 2m is measured. A measuring device comprises a capacitor storing voltage measured at a node 30. Voltage between both ends of the capacitor is dropped, as the distance between the terminal and a transponder increases. Voltage stored in the capacitor is sent to the processor of the terminal 1'.

公开(公告)号：JP2000353712A

公开(公告)日：2000-12-19

申请号：JP2000137263

申请日：2000-05-10

Applicant: ST MICROELECTRONICS SA

Inventor： JOSSE EMILE

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/50

Abstract: PROBLEM TO BE SOLVED: To obtain the packaging method of a chip formed on a semiconductor wafer with an electrically contacting part on both surfaces. SOLUTION: This packaging method contains a stage, where a conductive region 8 is provided on the first surface of a wafer, a stage where the first thick plate 10 of electric insulating material is adhered to the first surface, a stage where the wafer is etched from the second surface of the wafer with which a chip is prescribed, a stage where the conductive track 12, extending from the contact part 11 of the second surface to a conductive region is deposited, a stage where the second surface is covered by the second thick plate 14 and a fixing cap is formed by an insulating filling material 13 between the first thick plate and the second thick plate, and a stage where the conductive material, extending in track form to the surface of the first thick plate, is deposited on the conductive region.

公开(公告)号：JP2000341171A

公开(公告)日：2000-12-08

申请号：JP2000104891

申请日：2000-04-06

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  BARDOUILLET MICHEL ,  ENGUENT JEAN-PIERRE

IPC: G01S13/74 ,  G06K7/00 ,  G06K19/07 ,  H04B1/59 ,  H04B5/02

Abstract: PROBLEM TO BE SOLVED: To reduce or minimize thermal effect relating to remote power supply to a transponder by a read/write terminal by detuning the oscillation circuits of a terminal and/or the transponder, when they are in a very closely coupled relation. SOLUTION: A read/write terminal 1' of an electromagnetic transponder is equipped with a means for causing an oscillation circuit to be detuned from the carrier frequency. The terminal 1' includes the oscillation circuit, which is located between the output terminal 2p of an amplifier, i.e., an antenna coupler 3 and a terminal 2m with a reference potential and composed of a capacity component 24, a resistance R1, and a series antenna L1. Then the phase of the current of the antenna L1 is adjusted with respect to a reference signal REF. This adjustment is an adjustment of a high-frequency signal, i.e., a carrier signal corresponding to a signal TX having no transmission data and carried out by varying the capacitance C1 of the oscillation circuit of the terminal 1' and holding the antenna current at constant phase relation with the reference signal REF.

公开(公告)号：JP2000164738A

公开(公告)日：2000-06-16

申请号：JP33768899

申请日：1999-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： LAURENS MICHEL

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To reduce manufacturing step numbers and improve quality by etching a base Si outside a useful region, while leaving specified position on a thin oxide, forming collector contact regions at the same time as the drain injection of n-channel MOS transistors, and injecting in p-type base contact regions, at the same time as the drain-source implantation of p-channel MOS transistors. SOLUTION: Emitter-polysilicon layer 62 and a base Si layer 54 are etched, projecting parts 64 are left at normal positions on thick oxide regions to form base contact recovery regions, an N dopant contained in the polysilicon layer 62 diffuses slightly in an epitaxial layer 55 to form emitter regions 65, spacers 71 are formed at n-channel MOS transistors, spacers 72 are formed at the ends of the polysilicon layer 62, spacers 73 are formed at the ends of the base Si layer, the spacers 72 restricts the P injection from overdoping the extensions 64, and the base contact recovery regions are formed at the same time as forming the drain-sources of p-channel MOS transistors.

公开(公告)号：JP2000100925A

公开(公告)日：2000-04-07

申请号：JP24739199

申请日：1999-09-01

Applicant: ST MICROELECTRONICS SA

Inventor： DUCLOS FRANCK

IPC: H01L29/74 ,  H01L21/74 ,  H01L21/761 ,  H01L21/822 ,  H01L27/06 ,  H01L27/08 ,  H01L21/06

Abstract: PROBLEM TO BE SOLVED: To provide an insulation wall for isolation of an element having a small surface occupation area of a semiconductor and a small leakage current. SOLUTION: The fundamental element is formed in the first conductivity type semiconductor wafers 61 and 62. At least one fundamental element in a wafer functions at high current density, the second conductivity type insulating wall, where the fundamental element is isolated, has at least two fundamental walls 63 and 64 to be isolated on the part of wafer material, and the above- mentioned part is coupled to fundamental potential.

公开(公告)号：JP2000031155A

公开(公告)日：2000-01-28

申请号：JP15604999

申请日：1999-06-03

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To reduce low frequency noise while sustaining accurate current amplification factor by obtaining an emitter region of single crystal silicon touching the upper layer of a stack, e.g. silicon of an upper encapsulation layer of the stack, directly on a window. SOLUTION: On a silicon substrate 1, a buried extrinsic collector layer 2 doped with n+ by implanting arsenic and two buried layers 3 similarly doped with p+ are formed and a thick n-type single crystal silicon layer 4 is grown epitaxially. Subsequently, an amorphous silicon layer 17 is deposited on a semiconductor block thus formed and etched above an oxide layer 6 to form a window 170 which is then subjected to desorption. Thereafter, a stack 8 is formed, a silicon dioxide layer 9 and a silicon nitride layer 10 are deposited thereon and then the layers 9, 10 are removed from a desired zone to obtain an emitter, i.e., an emitter window 800.

公开(公告)号：JPH11354537A

公开(公告)日：1999-12-24

申请号：JP15606599

申请日：1999-06-03

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHARY SCHWARZMANN

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To increase the operating speed of a transistor, by executing the injection of a first dopant into the intrinsic collector of the transistor before nonselective epitaxy and the injection of a second dopant into the inner part of the collector at a smaller injected amount and with lower energy than the first dopant through an epitaxially grown stack. SOLUTION: The operating speed of a transistor is the value of the frequency (cut-off frequency of the current amplification factor) of the transistor and the value of the maximum oscillation frequency. The injection of a first dopant into an intrinsic collector 4 in a silicon substrate 1 is executed before the formation of a stack 8 which is formed in an intrinsic base and this injection is high- energy injection. The injection of a second dopant into the collector 4 is executed through an epitaxial base and the injected amount of the second dopant is 1/10 as small as that of the first dopant. Therefore, the defect level in the stack 8 becomes very low and, as a result, a thinner intrinsic base can be obtained and the speed of the transistor increases accordingly.