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公开(公告)号：KR100910527B1
公开(公告)日：2009-07-31
申请号：KR1020070098102
申请日：2007-09-28
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: 용량 조절형 적층형 칩 캐패시터는 복수의 유전체층이 적층되어 형성된 커패시터 본체를 포함한다. 복수 쌍의 제1 및 제2 내부 전극은 상기 커패시터 본체 내에서 상기 유전체층을 사이에 두고 서로 다른 극성의 내부 전극이 서로 대향하도록 교대로 배치된다. 복수 쌍의 제1 및 제2 외부 전극은 상기 제1 및 제2 내부 전극에 연결될 수 있도록 상기 커패시터 본체의 표면에 형성된다.
상기 제1 및 제2 내부 전극은 적어도 한 쌍의 제1 및 제2 내부전극을 갖는 복수의 그룹으로 구분되며, 상기 각 그룹의 제1 및 제2 내부 전극은 서로 다른 쌍의 제1 및 제2 외부 전극에 각각 연결된다. 이로써, 외부 전원라인에 연결되는 제1 및 제2 외부 전극의 선택에 따라 적어도 다른 2개의 용량값을 가질 수 있다.
적층형 칩 커패시터(MLCC), ESR, ESL-
公开(公告)号：KR1020090059748A
公开(公告)日：2009-06-11
申请号：KR1020070126771
申请日：2007-12-07
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: A multilayer chip capacitor is provided to improve stability of a power circuit by maintaining a proper ESR(Equivalent Series Resistance) and a low ESL(Equivalent Series Inductance). A multilayer chip capacitor(200) includes a capacitor main body(201), a plurality of inner electrodes, and a plurality of outer electrodes(231-238). The capacitor main body is formed by laminating a plurality of dielectric layers. A bottom surface(A) of the capacitor is a mounting surface. A plurality of inner electrodes is faced inside the capacitor main body. The dielectric layer is positioned between the inner electrodes. Each inner electrode has one lead drawn into the bottom surface of the capacitor main body and one lead drawn into a top surface(B) of the capacitor main body. A plurality of outer electrodes is formed on the top surface and the bottom surface of the capacitor main body. Each outer electrode is connected to the corresponding inner electrode through the lead.
Abstract translation: 提供了一种多层片式电容器，通过保持适当的ESR（等效串联电阻）和低ESL（等效串联电感）来提高电源电路的稳定性。 多层片状电容器（200）包括电容器主体（201），多个内部电极和多个外部电极（231〜238）。 电容器主体通过层叠多个电介质层而形成。 电容器的底面（A）是安装面。 多个内电极面对电容器主体内部。 电介质层位于内电极之间。 每个内部电极具有一个引线到电容器主体的底表面中的一个引线，一个引线被拉入电容器主体的顶表面（B）。 在电容器主体的顶表面和底表面上形成多个外电极。 每个外部电极通过引线连接到相应的内部电极。
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公开(公告)号：KR1020090032798A
公开(公告)日：2009-04-01
申请号：KR1020070098300
申请日：2007-09-28
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: A multilayer capacitor is provided to change an ESR(Equivalent Series Resistance) property according to a selection of an external electrode connected to an external power line. A multilayer capacitor(10) comprises a main body(11), a plurality of first internal electrodes, a plurality of second internal electrode, an internal connection conductor, a plurality of first external electrodes(18a,18b), and a plurality of second external electrodes(19a,19b). The main body is made of a plurality of dielectric layers. The first internal electrode and the second internal electrode are arranged inside the main body by turns. The internal electrodes of different polarity are faced each other. The internal connection conductor is adjacent to the internal electrode of different polarity. The first external electrode and the second external electrode are formed on a surface of the main body. The internal connection conductor is connected to the external electrode of identical polarity. A plurality of internal electrodes of a polarity such as the internal connection conductor is divided into a plurality of groups. Each group includes at least one internal electrode. The internal electrode of each group is connected to the external electrode of identical polarity, and is connected to the internal connection conductor through the external electrode.
Abstract translation: 根据连接到外部电力线的外部电极的选择，提供层叠电容器来改变ESR（等效串联电阻）特性。 多层电容器（10）包括主体（11），多个第一内部电极，多个第二内部电极，内部连接导体，多个第一外部电极（18a，18b）和多个第二外部电极 外部电极（19a，19b）。 主体由多个电介质层制成。 第一内部电极和第二内部电极轮流配置在主体的内部。 不同极性的内部电极相互面对。 内部连接导体与不同极性的内部电极相邻。 第一外部电极和第二外部电极形成在主体的表面上。 内部连接导体与极性相同的外部电极连接。 诸如内部连接导体的极性的多个内部电极被分成多个组。 每个组包括至少一个内部电极。 每组的内部电极连接到相同极性的外部电极，并通过外部电极连接到内部连接导体。
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公开(公告)号：KR1020090032797A
公开(公告)日：2009-04-01
申请号：KR1020070098299
申请日：2007-09-28
Applicant: 삼성전기주식회사
IPC: H01G4/30
CPC classification number: H01G4/228
Abstract: A multilayer capacitor is provided to perform a controllable ESR(Equivalent Series Resistance) and a low ESL(Equivalent Series Inductance) by improving a structure of a capacitor without a change of electrode material. A multilayer capacitor comprises a main body, a plurality of first internal electrodes(14), a plurality of second internal electrodes(15), internal connection conductors(12,13), a plurality of first external electrodes, and a plurality of second external electrodes. The main body has a first surface and a second surface. The first surface is faced with the second surface. The first surface is provided as a mounting surface. The first internal electrode and the second internal electrode are arranged inside the main body by turns in between dielectric layers. The internal electrodes of opposite polarity are faced each other. The internal connection conductor is adjacent to the internal electrode of opposite polarity. The first external electrode and the second external electrode are formed on the first surface and the second surface. The external electrode of a polarity such as the internal connection conductor includes at least one external terminal and at least one external connection conductor. The external terminal is formed on the first surface of the main body, and is connected to the internal connection conductor. The external connection conductor is formed on the second surface of the main body, and connects the internal electrode of an identical polarity to an internal connection conductor.
Abstract translation: 通过改善电容器的结构而不改变电极材料，提供了层叠电容器来执行可控ESR（等效串联电阻）和低ESL（等效串联电感）。 一种多层电容器包括主体，多个第一内部电极（14），多个第二内部电极（15），内部连接导体（12,13），多个第一外部电极和多个第二外部电极 电极。 主体具有第一表面和第二表面。 第一表面面对第二表面。 第一表面设置为安装表面。 第一内部电极和第二内部电极在电介质层之间轮流布置在主体内部。 相反极性的内部电极相互面对。 内部连接导体与相反极性的内部电极相邻。 第一外部电极和第二外部电极形成在第一表面和第二表面上。 诸如内部连接导体的极性的外部电极包括至少一个外部端子和至少一个外部连接导体。 外部端子形成在主体的第一表面上并连接到内部连接导体。 外部连接导体形成在主体的第二表面上，并且将具有相同极性的内部电极连接到内部连接导体。
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公开(公告)号：KR1020090032767A
公开(公告)日：2009-04-01
申请号：KR1020070098254
申请日：2007-09-28
Applicant: 삼성전기주식회사
CPC classification number: H05K1/162 , H01G4/33 , H05K1/185 , H05K2201/0175
Abstract: An embedded thin film capacitor is provided to improve an equivalent series inductance property by improving a magnetic flux offset effect due to a reverse current route. An embedded thin film capacitor comprises a thin film capacitor part(25), a plurality of first outer terminal part(27'), and a plurality of second outer terminal part(28'). The thin film capacitor part is positioned inside an insulating substrate, includes a first electrode layer(21), a dielectric film, and a second electrode layer, and is formed into a rectangular structure having two short sides and two long sides. The first outer terminal part and the second outer terminal part are respectively connected to the first electrode layer and the second electrode layer, and are arranged according to two long sides of the thin film capacitor part by turns.
Abstract translation: 提供一种嵌入式薄膜电容器，通过改善由于反向电流路径引起的磁通量偏移效应来提高等效的串联电感特性。 嵌入式薄膜电容器包括薄膜电容器部分（25），多个第一外部端子部分（27'）和多个第二外部端子部分（28'）。 薄膜电容器部分位于绝缘基板的内部，包括第一电极层（21），电介质膜和第二电极层，并且形成为具有两个短边和两个长边的矩形结构。 第一外部端子部分和第二外部端子部分分别连接到第一电极层和第二电极层，并且依次沿着薄膜电容器的两个长边布置。
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Patent Agency Ranking
公开(公告)号：KR1020090022878A
公开(公告)日：2009-03-04
申请号：KR1020070088544
申请日：2007-08-31
Applicant: 삼성전기주식회사
IPC: H01G4/30
CPC classification number: H01G4/232 , H01G4/012 , H01G4/30 , H01G4/385 , H05K1/0231 , H05K1/113 , H05K2201/09309 , H05K2201/09772 , H05K2201/0979 , H05K2201/10015 , H05K2201/10636 , Y02P70/611
Abstract: A multilayer chip capacitor, a circuit board device including the same, and a circuit board are provided to perform high ESR(Equivalent Series Resistance) and low ESL(Equivalent Series Inductance) by low maintaining impedance of an electric power distribution network in a large frequency range. A capacitor main body(110) includes a first capacitor part and a second capacitor part. The first capacitor part includes at least a pair of first and second inner electrodes. The first and the second inner electrodes are faced inside the main body. A dielectric layer is positioned between the first inner electrode and the second inner electrode. The first and the second inner electrodes have different polarity. The second capacitor part includes a third and a fourth inner electrodes. The third and the fourth electrodes are faced inside the main body. The dielectric layer is positioned between the third inner electrode and the fourth inner electrode. The third and the fourth electrodes have different polarity. A first ~ a fourth outer electrodes(131~134) are respectively connected to the first ~ the fourth inner electrodes. An ESL of the first capacitor part is lower than an ESL of the second capacitor part. An ESR of the first capacitor part is higher than an ESR of the second capacitor part.
Abstract translation: 提供一种多层片状电容器，包括该电路板的电路板装置和电路板，以便通过在大频率下配置电力网的低维持电阻来执行高ESR（等效串联电阻）和低ESL（等效串联电感） 范围。 电容器主体（110）包括第一电容器部分和第二电容器部分。 第一电容器部分包括至少一对第一和第二内部电极。 第一和第二内部电极面对主体内部。 电介质层位于第一内电极和第二内电极之间。 第一和第二内部电极具有不同的极性。 第二电容器部分包括第三和第四内部电极。 第三和第四电极面对主体内部。 电介质层位于第三内电极和第四内电极之间。 第三和第四电极具有不同的极性。 第一〜第四外部电极（131〜134）分别与第一〜第四内部电极连接。 第一电容器部分的ESL低于第二电容器部分的ESL。 第一电容器部分的ESR高于第二电容器部分的ESR。
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公开(公告)号：KR1020090019251A
公开(公告)日：2009-02-25
申请号：KR1020070083545
申请日：2007-08-20
Applicant: 삼성전기주식회사
IPC: H01F27/00
CPC classification number: H01F17/0013 , H01F3/14 , H01F17/04
Abstract: A laminated inductor is provided to improve a superposed property of a DC bias by adopting a magnetic layer as a main material and a magnetic gap as a non-magnetic conductor. A laminated inductor(10) includes a main body(11), a coil part(12), a first and second external electrodes(15a,15b), and a non-magnetic conductor(14). A plurality of magnetic layers are laminated on the main body. The coil part includes a plurality of conductor patterns and a plurality of conductive vias. The conductor patterns are formed on the magnetic layers. The first and second external electrodes are formed on an external surface of the main body and are connected with both ends of the coil part. The non-magnetic conductor is formed on at least one of the magnetic layers in order to lessen magnetic saturation due to superposed DC(Direct Current) generated the coil part.
Abstract translation: 提供层叠电感器，通过采用磁性层作为主要材料和磁隙作为非磁性导体来提高DC偏压的叠加特性。 叠层电感器（10）包括主体（11），线圈部分（12），第一和第二外部电极（15a，15b）和非磁性导体（14）。 多个磁性层层叠在主体上。 线圈部分包括多个导体图案和多个导电通孔。 导体图案形成在磁性层上。 第一外部电极和第二外部电极形成在主体的外表面上并且与线圈部分的两端连接。 非磁性导体形成在至少一个磁性层上，以便由于产生线圈部分的叠加DC（直流）而减小磁饱和。
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公开(公告)号：KR1020080079125A
公开(公告)日：2008-08-29
申请号：KR1020070019232
申请日：2007-02-26
Applicant: 삼성전기주식회사
CPC classification number: H01G4/232 , H01G2/06 , H01G4/38 , H01L23/50 , H01L2924/0002 , H01L2924/00
Abstract: An integrated multilayer chip capacitor module and an integrated circuit apparatus having the same are provided to reduce power network impedance in both high and low frequency regions by increasing packaging density of capacitors and to stabilize a power circuit. In an integrated multilayer chip capacitor module(200), a plurality of multilayer chip capacitors(20-1 to 20-4) are horizontally arranged. A capacitor support unit(25) receives the plurality of multilayer chip capacitors. Each of the multilayer chip capacitors has a rectangular parallelepiped-shaped capacitor body(21) and a plurality of first and second external electrodes(22a-22d) formed on at least two side surfaces of the capacitor body. The opposite external electrodes of the adjacent multilayer chip capacitors are electrically connected to each other by conductive adhesive material.
Abstract translation: 提供一体化多层片状电容器模块及其集成电路装置，通过提高电容器的封装密度和稳定电源电路来降低高频和低频区域中的电力网络阻抗。 在集成多层片状电容器模块（200）中，水平地配置有多个多层片状电容器（20-1〜20-4）。 电容器支撑单元（25）接收多个多层片状电容器。 每个多层片状电容器具有形成在电容器主体的至少两个侧表面上的长方体状电容器本体（21）和多个第一外部电极（22a-22d）。 相邻的多层片状电容器的相对的外部电极通过导电粘合剂材料彼此电连接。
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公开(公告)号：KR1020070109145A
公开(公告)日：2007-11-15
申请号：KR1020060041710
申请日：2006-05-09
Applicant: 삼성전기주식회사
Abstract: A multilayer chip capacitor is provided to facilitate the lamination of an inner electrode in the chip capacitor by using only two inner electrode patterns for manufacturing the chip capacitor. A capacitor body includes plural dielectric layers. First and second inner electrode layers(160,170) are separated from the dielectric layer inside the capacitor body. The outer electrode is formed on an outer surface of the capacitor and electrically connected to the inner electrode layer. Each of the first and second inner electrode layers is separated into more than three electrode plates. Each of the electrode plate includes first and second leads for coupling the electrode plate with the outer electrode. Leads of the first inner electrode layer are alternatively arranged to be adjacent to leads of the second inner electrode layer. The adjacent leads of the first and second electrode layer have different polarities.
Abstract translation: 提供了一种多层片状电容器，以通过仅使用两个用于制造芯片电容器的内部电极图案来促进片状电容器中的内部电极层压。 电容器主体包括多个电介质层。 第一和第二内部电极层（160,170）与电容器体内部的电介质层分离。 外电极形成在电容器的外表面上并与内电极层电连接。 第一和第二内部电极层中的每一个分离成多于三个电极板。 每个电极板包括用于将电极板与外部电极耦合的第一和第二引线。 第一内部电极层的引线交替地布置成与第二内部电极层的引线相邻。 第一和第二电极层的相邻引线具有不同的极性。
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公开(公告)号：KR100755654B1
公开(公告)日：2007-09-04
申请号：KR1020060052020
申请日：2006-06-09
Applicant: 삼성전기주식회사
Abstract: A multilayer ceramic capacitor with controllable ESR(Equivalent Series Resistance) characteristics is provided to control ESR characteristics and to prevent IR degradation and moisture-proof failure due to permeation of a plating solution. In a multilayer ceramic capacitor(100), a ceramic lamination includes a dielectric layer(10) and a number of internal electrodes(20,30) arranged between the dielectric layers. An external electrode(50) is formed on both ends of the ceramic lamination. A resistor layer(70) is formed on the external electrode, and includes conductive metal element forming the external electrode.
Abstract translation: 提供具有可控ESR（等效串联电阻）特性的多层陶瓷电容器，以控制ESR特性，并防止由于电镀液渗透导致的IR降解和防潮失效。 在多层陶瓷电容器（100）中，陶瓷层叠体包括介电层（10）和布置在电介质层之间的多个内部电极（20,30）。 在陶瓷层叠体的两端形成有外部电极（50）。 在外部电极上形成电阻层（70），并且包括形成外部电极的导电金属元件。
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