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公开(公告)号：KR1020110032158A
公开(公告)日：2011-03-30
申请号：KR1020090089504
申请日：2009-09-22
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/11
Abstract: PURPOSE: A wiring structure of a semiconductor chip package and a method for manufacturing the same are provided to remove thermal or mechanical impact in a package process by including a first protective layer having surface illuminance. CONSTITUTION: In a wiring structure of a semiconductor chip package and a method for manufacturing the same, a chip pad(111) inputs and outputs a signal to and from a semiconductor chip A rewiring pattern(113) is electrically connected to the chip pad. A protective film covers at least one of the chip pad and the rewiring pattern and has surface illuminance. The protective film has a first protective layer(112) covering the chip pad. A first protective film exposes a part of the chip pad to outside.
Abstract translation: 目的：提供半导体芯片封装的布线结构及其制造方法，以通过包括具有表面照度的第一保护层来消除封装工艺中的热或机械冲击。 构成：在半导体芯片封装的布线结构及其制造方法中，与半导体芯片A的输入和输出信号的芯片焊盘（111）重新布线图案（113）电连接到芯片焊盘。 保护膜覆盖芯片焊盘和重新布线图案中的至少一个并具有表面照度。 保护膜具有覆盖芯片焊盘的第一保护层（112）。 第一保护膜将芯片垫的一部分暴露于外部。
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公开(公告)号：KR1020110018629A
公开(公告)日：2011-02-24
申请号：KR1020090076190
申请日：2009-08-18
Applicant: 삼성전기주식회사
IPC: H01L21/60 , H01L21/288
CPC classification number: H01L24/03 , H01L24/05 , H01L2224/0231 , H01L2224/0239 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322
Abstract: 본 발명은 기판의 적어도 일 영역에 도전성 패드를 형성하는 단계, 상기 기판 상에 상기 도전성 패드를 노출하는 개구부를 갖는 제1 절연층을 형성하는 단계, 상기 제1 절연층 상에 상기 도전성 패드와 접속하는 배선층을 형성하는 단계, 상기 배선층 상에 상기 배선층을 밀봉하는 도전성 확산 방지층을 형성하는 단계, 상기 확산 방지층 상에 상기 확산 방지층의 일부를 노출하는 콘택홀을 갖는 제2 절연층을 형성하는 단계 및 상기 콘택홀에 범프 패드를 형성하는 단계를 포함하는 웨이퍼 레벨 디바이스 패키지의 제조 방법을 제공한다.
본 발명에 따르면, 범프 패드 및 확산 방지층 형성을 위한 복잡한 포토 리소그래피 공정을 간단한 무전해 도금법으로 대체함으로써 또한 공정 시간 및 공정 비용의 절감이 가능한 웨이퍼 레벨 디바이스 패키지의 제조 방법을 제공할 수 있다.
반도체, 웨이퍼, 재배선층, 범프, 도금-
公开(公告)号：KR1020100112866A
公开(公告)日：2010-10-20
申请号：KR1020090031373
申请日：2009-04-10
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/04105 , H01L2224/19 , H01L2224/20 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/00012
Abstract: PURPOSE: A semiconductor package with a heat sink and a manufacturing method thereof are provided to improve resistance against warpage by including a hard heat sink made of metals with thermal conductivity to replace a reconstruction layer. CONSTITUTION: A support layer is formed on the upper side of a heat sink(100). A semiconductor chip(500) is arranged in a cavity on the upper side of the heat sink. A first passivation layer(700) is formed on the upper sides of the support layer and the semiconductor chip. A rerouting layer(800) is electrically connected to a bonding pad. A solder ball(900) is arranged on the upper side of the rerouting layer.
Abstract translation: 目的：提供具有散热器的半导体封装及其制造方法，以通过包括由具有导热性的金属制成的硬散热器来替代重建层来提高抗翘曲性。 构成：在散热器（100）的上侧形成支撑层。 半导体芯片（500）布置在散热器的上侧的空腔中。 第一钝化层（700）形成在支撑层和半导体芯片的上侧。 重路由层（800）电连接到接合焊盘。 焊接球（900）布置在重新布线层的上侧。
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公开(公告)号：KR1020100090883A
公开(公告)日：2010-08-18
申请号：KR1020090010093
申请日：2009-02-09
Applicant: 삼성전기주식회사
CPC classification number: H01L24/96 , H01L21/568 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/92 , H01L2924/01033 , H01L2924/01059 , H01L2924/01075 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/96 , H01L2224/82 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: A method for manufacturing a wafer level package is provided to prevent the warpage of a package during the curing process of a molding material by forming the molding material in a space between pluralities of chips. CONSTITUTION: A plurality of chips(110) is mounted on one side of a supporting unit. A molding material(120) is formed in a space between the pluralities of chips. The molding material is formed by a printing method using a printing mask. The printing mask opens the space between the pluralities of chips. The supporting unit is eliminated. An insulating layer including a re-distribution wiring(140) is formed on one side of the molding material including the chip. The re-distribution wiring is connected with the pads of the chips. An external connecting unit is formed to be connected with the re-distribution wiring.
Abstract translation: 目的：提供一种制造晶片级封装的方法，以通过在多个芯片之间的空间中形成模制材料来防止在模制材料的固化过程中封装的翘曲。 构成：多个芯片（110）安装在支撑单元的一侧。 模制材料（120）形成在多个芯片之间的空间中。 成型材料通过使用印刷掩模的印刷方法形成。 打印掩模打开多个芯片之间的空间。 支持单元被消除。 在包括芯片的成型材料的一侧上形成包括再分配布线（140）的绝缘层。 再分配线路与芯片的焊盘连接。 外部连接单元形成为与再分配配线连接。
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公开(公告)号：KR1020100087933A
公开(公告)日：2010-08-06
申请号：KR1020090007004
申请日：2009-01-29
Applicant: 삼성전기주식회사
CPC classification number: H01L24/75 , H01L24/83 , H01L2224/83192
Abstract: PURPOSE: A die attach device and a method thereof are provided to improve a recognition rate and reduce a pick-up defect by using the penetrating power of an infrared camera. CONSTITUTION: A pick-up head(110) absorbs a die from a wafer and attaches it to a substrate. An infrared camera(130) recognizes the pad position and corner position of the die transferred with the pick-up head. A controller controls the pick-up head according to the pad position of the die which is measured with the infrared camera. An auxiliary visual camera(140) recognizes the pad position of the die in the lower part of the die which is transferred with the pick-up head. The pick-up head picks up the die with a face-up state.
Abstract translation: 目的：提供一种芯片连接装置及其方法，以通过使用红外相机的穿透力来提高识别率并减少拾取缺陷。 构成：拾取头（110）从晶片吸收模具并将其附着到基板上。 红外摄像机（130）识别用拾取头传送的模具的垫位置和角位置。 控制器根据用红外摄像机测量的模具的垫位置来控制拾取头。 辅助视觉摄像机（140）识别在与拾取头一起传送的模具的下部中的模具的衬垫位置。 拾起头以面朝上的状态拾起模具。
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Patent Agency Ranking
公开(公告)号：KR1020100071492A
公开(公告)日：2010-06-29
申请号：KR1020080130227
申请日：2008-12-19
Applicant: 삼성전기주식회사
IPC: H01L21/60
CPC classification number: H01L2224/11 , H01L2924/14 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: A liquid reflow method is provided to increase a solder bump by buoyancy inside a liquid bath by performing the reflow after the substrate is immerged in the liquid bath. CONSTITUTION: A substrate with a circuit pattern and a pad(103) is provided. A mask exposing only pad is located on the upper side of the mask. A solder paste is printed on the pad. The substrate is immersed in a liquid path(120a). The reflow is performed inside the liquid bath. A solder paste of the substrate is changed into a solder bump(140).
Abstract translation: 目的：提供液体回流方法，通过在将基板浸入液槽中后进行回流，通过浮液在液槽内增加焊料凸块。 构成：提供具有电路图案和衬垫（103）的衬底。 仅掩模的掩模位于掩模的上侧。 焊盘上印有焊膏。 将衬底浸入液体通道（120a）中。 回流焊在液槽内进行。 衬底的焊膏变成焊料凸块（140）。
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公开(公告)号：KR1020100071485A
公开(公告)日：2010-06-29
申请号：KR1020080130219
申请日：2008-12-19
Applicant: 삼성전기주식회사
IPC: H01L21/78 , H01L21/301
CPC classification number: H01L21/561 , H01L23/24 , H01L23/3121 , H01L24/94 , H01L2924/09701 , H01L2924/181 , H01L2924/3511 , H01L2924/00
Abstract: PURPOSE: A method for manufacturing a wafer level package is provided to reduce stress due to thermal expansion coefficient differences between an encapsulating material and a substrate wafer. CONSTITUTION: A plurality of pads(113), a chip(115), a dicing line are formed on a substrate wafer(110). An external connection unit(120) is formed on the pad. A resin is coated on the dicing line. An encapsulating material(150) is coated on the chip positioned between resins. The resin coated on the dicing line is removed.
Abstract translation: 目的：提供一种用于制造晶片级封装的方法，以减少由于封装材料和衬底晶片之间的热膨胀系数差引起的应力。 构成：在基板晶片（110）上形成多个焊盘（113），芯片（115），切割线。 外部连接单元（120）形成在垫上。 在切割线上涂覆树脂。 将封装材料（150）涂覆在位于树脂之间的芯片上。 去除涂覆在切割线上的树脂。
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公开(公告)号：KR1020100068650A
公开(公告)日：2010-06-24
申请号：KR1020080127079
申请日：2008-12-15
Applicant: 삼성전기주식회사
CPC classification number: H01L25/0652 , H01L2224/16145 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: PURPOSE: A semiconductor stacked package is provided to enhance electrical reliability by comprising a rearranged wiring layer between stacked semiconductor chips in order to shorten the length of a wire in a wire bonding process. CONSTITUTION: A first semiconductor chip(110) is mounted on a printed circuit board. A second semiconductor chip(120) is mounted on the printed circuit board, parallel with the first semiconductor chip. A first rearranged wiring layer(140) is arranged on the first semiconductor chip. A second rearranged wiring layer(150) is arranged on the second semiconductor chip. A third semiconductor chip(130) is electrically connected to the first rearranged wiring layer and the second rearranged wiring layer.
Abstract translation: 目的：提供半导体堆叠封装以通过在堆叠的半导体芯片之间包括重新布置的布线层来提高电可靠性，以便在引线接合工艺中缩短导线的长度。 构成：第一半导体芯片（110）安装在印刷电路板上。 第二半导体芯片（120）安装在印刷电路板上，与第一半导体芯片平行。 第一重排布线层（140）布置在第一半导体芯片上。 第二重排布线层（150）布置在第二半导体芯片上。 第三半导体芯片（130）电连接到第一重排布线层和第二重排布线层。
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公开(公告)号：KR1020090120216A
公开(公告)日：2009-11-24
申请号：KR1020080046144
申请日：2008-05-19
Applicant: 삼성전기주식회사
IPC: H01L23/48
CPC classification number: H01L2224/10
Abstract: PURPOSE: A wafer level chip size package and a manufacturing method thereof are provided to alleviating the stress concentration applied to a solder ball due to the difference between coefficients of thermal expansion of a resin sealing unit and the solder ball by forming a stress relaxation unit having a coefficient of thermal expansion lower than the resin sealing unit. CONSTITUTION: A wafer level chip size package(30) includes a semiconductor chip, the first insulation layer, a re-wiring layer, the first solder ball, a stress relaxation unit, and a resin sealing unit. On the semiconductor chip, a bonding pad is formed. The first insulation layer is formed in an upper side of the semiconductor chip excepting for the bonding pad. One end of the re-wring layer is connected to a bonding pad on the first insulation layer and the other end has a connection pad. The first solder ball(39) is formed in the connection pad. The stress relaxation unit is formed as surrounding the outer side of the first solder ball. The resin sealing unit(40) is formed to seal the re-wiring layer, the first insulation layer and the first solder ball.
Abstract translation: 目的：提供晶片级芯片尺寸封装及其制造方法，以通过形成应力松弛单元，由于树脂密封单元和焊球之间的热膨胀系数的差异来减轻施加到焊球的应力集中，该应力松弛单元具有 热膨胀系数低于树脂密封单元。 构成：晶片级芯片尺寸封装（30）包括半导体芯片，第一绝缘层，再布线层，第一焊球，应力松弛单元和树脂密封单元。 在半导体芯片上形成接合焊盘。 除了焊盘之外，第一绝缘层形成在半导体芯片的上侧。 再缠绕层的一端连接到第一绝缘层上的接合焊盘，另一端具有连接焊盘。 第一焊球（39）形成在连接焊盘中。 应力松弛单元形成为围绕第一焊球的外侧。 树脂密封单元（40）形成为密封重新布线层，第一绝缘层和第一焊球。
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公开(公告)号：KR1020090120215A
公开(公告)日：2009-11-24
申请号：KR1020080046143
申请日：2008-05-19
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/16 , H01L2924/01079 , H01L23/31 , H01L21/3212 , H01L23/29 , H01L23/49816 , H01L23/522
Abstract: PURPOSE: A wafer level chip size package and a manufacturing method thereof are provided to reduce the waste of a protective layer by forming the first protective layer on a re-wiring layer and an insulating layer as much as the required height. CONSTITUTION: A wafer level chip size package(100) includes a semiconductor chip, an insulating layer, a re-wiring layer, a solder ball, and a protective layer. A bonding pad(102) is formed on the semiconductor chip(101). The insulating layer(104) is formed in an upper side of the semiconductor chip excepting for the bonding pad. One end of the re-wiring layer(106) is connected with the bonding pad and the other end is connected to the insulating layer. The solder ball(108) is formed in a connection pad. A protective layer(111) is formed so that the solder ball, re-wiring layer and insulating layer can be sealed. The protective layer is comprised of the first protective layer and the second protective layer. The first protective layer(111A) is formed in upper sides of the re-wiring layer and insulating layer. The second protective layer(111B) is formed as surrounding the outer surface of the solder ball.
Abstract translation: 目的：提供晶片级芯片尺寸封装及其制造方法，以通过在重新布线层和绝缘层上形成所需高度的方式来形成第一保护层来减少保护层的浪费。 构成：晶片级芯片尺寸封装（100）包括半导体芯片，绝缘层，再布线层，焊球和保护层。 在半导体芯片（101）上形成接合焊盘（102）。 绝缘层（104）形成在除了焊盘之外的半导体芯片的上侧。 再配线层（106）的一端与焊盘连接，另一端与绝缘层连接。 焊球（108）形成在连接焊盘中。 形成保护层（111），使得可以密封焊球，再布线层和绝缘层。 保护层由第一保护层和第二保护层构成。 第一保护层（111A）形成在再布线层和绝缘层的上侧。 第二保护层（111B）形成为围绕焊球的外表面。
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