Abstract:
The present invention relates to an infrared sensor module, which can improve only the transmittance of an infrared transmitting layer without a silicon layer and in which an infrared sensor is packaged in a vacuum, and a manufacturing method thereof. The infrared sensor module includes: a device wafer (10) with an infrared sensor (14) formed on a silicon substrate (12); a cap wafer (20) including an infrared transmitting layer (24) which becomes transparent in the infrared band; a spacer (30) interposed between the device wafer (10) and the cap wafer (20); and a binding material (40) combining the device wafer (10) with the cap wafer (20). According to the present invention, the infrared sensor module can obtain an improved infrared sensing effect by comprising only the infrared transmitting layer without a silicon layer which becomes opaque in the infrared band.
Abstract:
PURPOSE: A passive matrix-addressable memory device is provided to maintain data state stored at a memory cell by reducing a size of an interference voltage applied to a memory unit. CONSTITUTION: One parallel second electrode line(220) or more are formed to a cross direction with a first electrode line(210). A memory unit(100) is formed between the first and second electrode lines and includes electrically polarizable material showing hysteresis. A switch is formed between the memory unit and the first electrode line. The switch unit has increased current conductivity when the applied voltage is above a threshold voltage. A depolarization preventing unit is formed between the switch unit and the memory unit and prevents the depolarization on the interface between the switch unit and the memory. The depolarization preventing unit includes a metal material or electrical conductive polymer material.
Abstract:
본 발명은 적외선 검출기인 볼로메타에 관한 것으로서, 더욱 상세하게는 적외선 열에 의해 변화된 저항값을 읽을 때와 열흡수층의 잔열을 제거하기 위해 사용되는 신호 다리를 구비한 적외선 볼로메타에 관한 것이다. 본 발명에 따른 적외선 볼로메타는 보호층으로 코팅된 집적회로를 구비한 하부 기판; 적외선을 흡수하는 흡수층과, 상기 흡수층으로부터 흡수된 적외선 열에 의해 저항값이 변하는 저항체를 구비하고, 상기 하부 기판과 소정의 공간을 갖으며 서로 이격되어 있는 상부 기판; 상기 상부 기판를 기계적으로 지지하고, 상부 기판과 하부 기판을 연결하는 포스트(Post); 상기 하부 기판과 상부 기판 사이에서 상기 저항체로부터 하부 기판으로 신호를 전달하는 신호 다리; 상기 신호 다리를 상기 상부 기판과 전기적으로 온-오프되도록 구동하기 위하여 하부 기판 상면에 형성된 하부 전극; 및 상기 하부 기판 상면에 형성되고, 적외선 열의 흡수율을 증가시키기 위한 반사층을 포함하여 이루어진다.
Abstract:
PURPOSE: A smart signal obtaining circuit for suppressing a background current, compensating ununiformity, and recovering bad pixels is provided to compensate the background current after storing the background current of an infrared sensing element to simultaneously suppress the background current and compensate the ununiformity by additionally incorporating an ADC/DAC and a memory for preventing the error caused by the junction leakage current. CONSTITUTION: In a smart signal obtaining circuit for suppressing a background current, compensating ununiformity, and recovering bad pixels, a gate of a first PMOSFET(Mskim) and a drain of a second PMOSFET(Mmem) are connected to a source of a third PMOSFET(Msel) to store a gate voltage of the first PMOSFET. The third PMOSFET has a gate of the third PMOSFET connected to Φmem, and a drain connected to an ADC/DAC via a BUSref. The ADC/DAC is connected to a memory(latch) by a BUSmem, so that a background current value stored to a current copier cell is digitalized and stored, and the gate voltage of the first PMOSFET is periodically reset.
Abstract:
PURPOSE: A smart signal obtaining circuit for suppressing a background current, compensating ununiformity, and recovering bad pixels is provided to compensate the background current after storing the background current of an infrared sensing element to simultaneously suppress the background current and compensate the ununiformity by additionally incorporating an ADC/DAC and a memory for preventing the error caused by the junction leakage current. CONSTITUTION: In a smart signal obtaining circuit for suppressing a background current, compensating ununiformity, and recovering bad pixels, a gate of a first PMOSFET(Mskim) and a drain of a second PMOSFET(Mmem) are connected to a source of a third PMOSFET(Msel) to store a gate voltage of the first PMOSFET. The third PMOSFET has a gate of the third PMOSFET connected to Φmem, and a drain connected to an ADC/DAC via a BUSref. The ADC/DAC is connected to a memory(latch) by a BUSmem, so that a background current value stored to a current copier cell is digitalized and stored, and the gate voltage of the first PMOSFET is periodically reset.