公开(公告)号：KR1019950008253B1

公开(公告)日：1995-07-26

申请号：KR1019920023351

申请日：1992-12-04

Applicant: 한국전자통신연구원

Inventor： 이정희 ,  박성호 ,  이해권 ,  강진영 ,  이용택

IPC: H01L29/80

Abstract: forming GaAs quasi-collector layer (7), GaAs collector layer (6), GaAs base layer (5), AlGaAs emitter layer (4), and GaAs ohmic contact layer (3) sequentailly; forming AlAs selective etching layer (2) and GaAs guiding layer (1) on the GaAs ohmic contact layer sequentially; etching the GaAs guiding layer, the AlAs selective etching layer, the GaAs ohmic contact layer, and AlGaAs emitter layer (4) to form inverse mesa structure; forming base ohmic contact layer (9) on the AlGaAs emitter layer; removing the GaAs guiding layer and the AlAs selective etching layer of the inverse mesa structure and spreading silicon oxide layer (10); forming emitter and collector ohmic contact metal layer (11) on the exposed quasi-collector layer and the GaAs ohmic contact layer; forming base ohmic contact metal layer (12) on the base ohmic contact layer; and forming metal layer (14) on the ohmic contact metal layers.

Abstract translation: 形成GaAs准集电极层（7），GaAs集电极层（6），GaAs基极层（5），AlGaAs发射极层（4）和GaAs欧姆接触层（3）; 在GaAs欧姆接触层上依次形成AlAs选择性蚀刻层（2）和GaAs引导层（1）; 蚀刻GaAs引导层，AlAs选择性蚀刻层，GaAs欧姆接触层和AlGaAs发射极层（4）以形成逆台面结构; 在AlGaAs发射极层上形成基极欧姆接触层（9）; 去除反向台面结构的GaAs引导层和AlAs选择性蚀刻层，并扩展氧化硅层（10）; 在暴露的准集电极层和GaAs欧姆接触层上形成发射极和集电极欧姆接触金属层（11）; 在基极欧姆接触层上形成基极欧姆接触金属层（12）; 以及在欧姆接触金属层上形成金属层（14）。

公开(公告)号：KR1019940004274B1

公开(公告)日：1994-05-19

申请号：KR1019900021806

申请日：1990-12-26

Applicant: 한국전자통신연구원

Inventor： 이정희 ,  박성호 ,  이종람 ,  김진섭 ,  박형무

IPC: H01L29/80

Abstract: forming a first epitaxial layer 2 on a GaAs substrate 1 using molecular beam epitaxy; forming an insulating layer 3 by sequential deposition of a first AlGaAs 3b, GaAs 3c and a second AlGaAs 3a on first epitaxial layer 2, first AlGaAs layer 3b and second AlGaAs layer 3a are formed at the same temperature, and GaAs layer 3c is formed at the temperature lower than that of AlGaAs layer 3a,3b; forming an second epitaxial layer 4 on the insulating layer 3; selective etching second AlGaAs layer 3a, GaAs layer 3c and first Al GaAs layer 3b so as to expose first epitaxial layer 2 and second epitaxial layer 4a; forming a metal pattern 6 on an active region of each device; forming a predetermined photoresist pattern 5a on the surface of the substrate; forming an isolation region 7 in the vertical derection to the substrate by ion implanting into the substrate using the photoresist pattern 5a as mask, thereby to shut off the current between the the devices without damaging to the substrate.

Abstract translation: 使用分子束外延在GaAs衬底1上形成第一外延层2; 通过在第一外延层2上顺序沉积第一AlGaAs 3b，GaAs 3c和第二AlGaAs 3a来形成绝缘层3，在相同温度下形成第一AlGaAs层3b和第二AlGaAs层3a，并且形成GaAs层3c 温度低于AlGaAs层3a，3b; 在绝缘层3上形成第二外延层4; 选择性蚀刻第二AlGaAs层3a，GaAs层3c和第一Al GaAs层3b，以暴露第一外延层2和第二外延层4a; 在每个装置的有源区上形成金属图案6; 在所述基板的表面上形成预定的光致抗蚀剂图案5a; 通过使用光致抗蚀剂图案5a作为掩模将衬底中的离子注入到衬底中，在垂直于衬底的垂直方向上形成隔离区域7，从而切断器件之间的电流而不损坏衬底。

公开(公告)号：KR1019940004261B1

公开(公告)日：1994-05-19

申请号：KR1019900021810

申请日：1990-12-26

Applicant: 한국전자통신연구원

Inventor： 이종람 ,  박성호 ,  박철순 ,  김진섭 ,  박형무

IPC: H01L21/335

Abstract: forming a carrier channel layer 2 on a GaAs substrate 1; forming a passivation layer 3 and a GaAs semiconductor layer 4 on the overall surface of the carrier channel layer, and forming a substrate pattern with mesa shape; forming a insulating layer 5 on the GaAs layer 4; forming a gate insulating layer 5a by etching the insulating layer 5 and GaAs layer 4; forming a gate on the gate insulating layer 5a; forming a source region and drain region by selective implantation of silicon ion into the passivation layer 3; and forming a source 8 and drain 9 on the source region and drain region, thereby improving the operating speed and high frequency characteristics of the metal-insulator field effect transistor.

Abstract translation: 在GaAs衬底1上形成载流子通道层2; 在载流子通道层的整个表面上形成钝化层3和GaAs半导体层4，并形成台面形状的衬底图形; 在GaAs层4上形成绝缘层5; 通过蚀刻绝缘层5和GaAs层4形成栅极绝缘层5a; 在栅极绝缘层5a上形成栅极; 通过将硅离子选择性地注入到钝化层3中来形成源极区和漏极区; 并在源极区域和漏极区域上形成源极8和漏极9，从而提高金属 - 绝缘体场效应晶体管的工作速度和高频特性。

公开(公告)号：KR1019940004014B1

公开(公告)日：1994-05-10

申请号：KR1019910024772

申请日：1991-12-28

Applicant: 한국전자통신연구원

Inventor： 박성호 ,  강진영 ,  이용탁

IPC: H01L21/20

Abstract: electrically isolating the elements by mesa-etching the epitaxial growth layer including a cap layer laminated with GaAs layer, AlAs layer and GaAs layer; forming a source and a drain by forming a photoresist pattern and selectively vapor-depositing and heat-treating an ohmic metal layer; forming a depletion gate region by etching GaAs cap layer and an enhancement gate region by etching GaAs cap layer and AlAs cap layer in turn; and forming a depletion gate and enhancement gate by vapor-depositing gate metal on each rigion. The depletion and enhancement gates capable of exactly controlling a threshold voltage is simultaneously formed. Without the depreciation of electrical properties.

Abstract translation: 通过台面蚀刻包括层叠有GaAs层，AlAs层和GaAs层的覆盖层的外延生长层来电隔离元件; 通过形成光致抗蚀剂图案并选择性地气相沉积和热处理欧姆金属层来形成源极和漏极; 通过依次蚀刻GaAs覆盖层和AlAs覆盖层，通过蚀刻GaAs覆盖层和增强栅极区域来形成耗尽栅极区域; 以及通过在每个焊缝上气相沉积栅极金属来形成耗尽栅极和增强栅极。 同时形成能够精确控制阈值电压的耗尽和增强门。 没有电气特性的折旧。

公开(公告)号：KR100056112B1

公开(公告)日：1992-11-06

申请号：KR1019880017986

申请日：1988-12-30

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 박성호 ,  강봉구 ,  이영수 ,  김보우 ,  김진섭

IPC: H01L21/00

公开(公告)号：KR1019920013605A

公开(公告)日：1992-07-29

申请号：KR1019900021811

申请日：1990-12-26

Applicant: 한국전자통신연구원

Inventor： 이종람 ,  이정희 ,  박성호 ,  김진섭 ,  박형무

IPC: H01L21/31

Abstract: 내용 없음.

公开(公告)号：KR1019920013603A

公开(公告)日：1992-07-29

申请号：KR1019900021807

申请日：1990-12-26

Applicant: 한국전자통신연구원

Inventor： 이정희 ,  박성호 ,  이종람 ,  김진섭 ,  박형무

IPC: H01L21/335

公开(公告)号：KR1019920001914B1

公开(公告)日：1992-03-06

申请号：KR1019890012068

申请日：1989-08-24

Applicant: 한국전자통신연구원

Inventor： 이종람 ,  박성호 ,  맹성재 ,  김진섭

IPC: H01L23/52 ,  H01L27/04

Abstract: The metal wiring for a semiconductor element is formed by (A) forming a photosensitive film on the semiconductor substrate, (B) enhancing the stength of photosensitive film by low-temperature treating, (C) dipping the photosensitive film in monochlorobenzene, (D) recovering the strength of photosensitive film, (E) selectively exposing the photosensitive film, (F) high-temperature treating the film after developing, (G) depositing a metal layer on the upper side of the film, and (H) reproducing disired metal wiring by the lifting-off process.

Abstract translation: （A）在半导体基板上形成感光膜，（B）通过低温处理提高感光膜的长度，（C）将感光膜浸渍在一氯苯中，形成（D） 回收感光膜的强度，（E）选择性地曝光感光膜，（F）显影后对膜进行高温处理，（G）在膜的上侧沉积金属层，和（H）再现无色金属 通过起吊过程进行接线。

公开(公告)号：KR1019910008976B1

公开(公告)日：1991-10-26

申请号：KR1019880017985

申请日：1988-12-30

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 강봉구 ,  박성호 ,  이영수 ,  배남진 ,  임대섭

IPC: H01L21/30

Abstract: The generator using at manufacturing process of the semiconductor device comprises a L type wave guide tube guiding the microwave of 2.45 GHz, a cylindrical plasma generating chamber generating the high density plasma under vacuum of 10-3-10-5 Torr using ECR effects, magnetic coils generating the magnetic flux exciting the reacted gas supplied through the gas injection tube (5), a crystal plate passing the microwave energy, and metal grid accelerating the plasma vertically against to the semiconductor substrate.

Abstract translation: 在半导体器件的制造过程中使用的发生器包括引导2.45GHz的微波的L型波导管，使用ECR效应在10-3-10-5Torr的真空下产生高密度等离子体的圆柱形等离子体发生室，磁性 产生激励通过气体注入管（5）供应的反应气体的磁通线圈，通过微波能量的晶体板和垂直加速等离子体的金属网格抵靠半导体衬底。

公开(公告)号：KR1019910005399B1

公开(公告)日：1991-07-29

申请号：KR1019880011472

申请日：1988-09-05

Applicant: 한국전자통신연구원

Inventor： 심규환 ,  이재신 ,  박성호 ,  강진영

IPC: H01L29/76 ,  H01L29/78

Abstract: The self-aligned GaAs FET using double side wall process is manufactured by: depositing the oxide film (105) for outer side wall after forming a dummy gate (104); ion-implantation the n-type impurity after formign outer side wall (106) by dry etching; forming a inner side wall after depositing the oxide film for inner side wall; depositing the gate metal after removing the nitride film (103) of gate region; forming interconnection metal after depositing the oxide film and photoresist (110). The device is useful for high speed operation and has an advantage for reducing the charge capacity of source-gate and the resistance of source.

Abstract translation: 使用双面壁工艺的自对准GaAs FET通过：在形成虚拟栅极（104）之后沉积用于外侧壁的氧化物膜（105）; 通过干蚀刻离子注入形成外侧壁（106）后的n型杂质; 在沉积内壁氧化膜之后形成内侧壁; 在去除栅极区域的氮化物膜（103）之后沉积栅极金属; 在沉积氧化膜和光致抗蚀剂（110）之后形成互连金属。 该装置对于高速运行是有用的，并且具有减小源极的充电容量和源极电阻的优点。