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公开(公告)号：KR1020100072614A
公开(公告)日：2010-07-01
申请号：KR1020080131065
申请日：2008-12-22
Applicant: 한국전자통신연구원
CPC classification number: G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/171 , Y02D10/172 , Y02D50/20
Abstract: PURPOSE: A processor with low power is provided to activate at least one among core block, a memory, a peripheral block by responding to a signal which activates according to an address map, thereby preventing a power consumption. CONSTITUTION: A low power processor comprises a plurality of blocks(30,70), a memory(50), and a multi power control unit(10). The memory stores a command for controlling the plurality of blocks. According to an address, the multi power control unit generates a signal for activating at least one among the plurality of blocks. By responding to the activation signal, the multi power control unit provides a normal power voltage or reduction power voltage. A command is stored in a relevant address.
Abstract translation: 目的：提供低功耗的处理器，通过响应根据地址映射激活的信号来激活核心块，存储器，外围块中的至少一个，从而防止功耗。 构成：低功率处理器包括多个块（30,70），存储器（50）和多功率控制单元（10）。 存储器存储用于控制多个块的命令。 根据地址，多功率控制单元生成用于激活多个块中的至少一个的信号。 通过响应激活信号，多功率控制单元提供正常的电源电压或降低功率电压。 命令存储在相关地址中。
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公开(公告)号：KR1020100063620A
公开(公告)日：2010-06-11
申请号：KR1020090031777
申请日：2009-04-13
Applicant: 한국전자통신연구원
IPC: H04N19/147 , H04N19/103 , H04N19/51
CPC classification number: H04N19/567 , H04N19/105
Abstract: PURPOSE: An image processing apparatus is provided, which firstly decides the optimal encoding mode, and then, proceeds the other processes such as the motion estimation and compensation, quantization, the variable length coding and inverse quantization etc. CONSTITUTION: A control unit(101) stores the generated bit amount for the computation of the Rate Distortion cost value. The control unit transmits respectively the generated bit amount to a plurality of operation units(110,120,130,140). At least one among a plurality of operation units produces each degree of distorted value about a plurality of encoding modes. The control unit calculates each distorted cost value about a plurality of encoding modes by the calculated distorted value and the generated bit amount.
Abstract translation: 目的：提供一种图像处理装置，其首先确定最佳编码模式，然后进行诸如运动估计和补偿，量化，可变长度编码和反量化等的其他处理。构成：控制单元（101 ）存储用于计算速率失真成本值的生成位数。 控制单元将产生的位量分别发送到多个操作单元（110,120,130,140）。 多个操作单元中的至少一个产生关于多个编码模式的每个程度的失真值。 控制单元通过计算出的失真值和产生的位量来计算关于多个编码模式的每个失真成本值。
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公开(公告)号：KR1020090058657A
公开(公告)日：2009-06-10
申请号：KR1020070125348
申请日：2007-12-05
Applicant: 한국전자통신연구원
IPC: G06F7/57
CPC classification number: G06F7/57 , G06F7/5324 , G06F7/5338
Abstract: A reconfigurable arithmetic operator and a high efficiency processor with the same are provided to supply an arithmetic operator operating as an adder or a multiplier according to an instruction, thereby increasing hardware utilization. A reconfigurable arithmetic operator comprises a booth encoder(210), a partial product generator(220), a wallace tree circuit(230), the first register(241), the second register(242), the first MUX(251), the second MUX(252), and a CPA(Carry Propagation Adder)(260). The partial product generator generates a partial product based on encoded multiplier and multilplicand. The CPA performs an addition operation by using outputs of the first and second MUXs.
Abstract translation: 提供可重构算术运算器和具有该可重配算术运算器的高效处理器，以根据指令提供作为加法器或乘法器运算的算术运算器，从而增加硬件利用率。 可重构算术运算器包括展位编码器（210），部分乘积产生器（220），华莱士树电路（230），第一寄存器（241），第二寄存器（242），第一多路复用器（251） 第二MUX（252）和CPA（Carry Propagation Adder）（260）。 部分产品生成器基于编码乘数和多项式生成部分乘积。 CPA通过使用第一和第二MUX的输出执行相加操作。
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公开(公告)号：KR1020090055765A
公开(公告)日：2009-06-03
申请号：KR1020070122575
申请日：2007-11-29
Applicant: 한국전자통신연구원
IPC: G06F9/46
CPC classification number: G06F15/8007 , G06F9/30181 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
Abstract: An SIMD processor for processing multimedia data for being operated and an operation method using the same are provided to improve the operation efficiency of the multimedia data by allocating the control right of a control unit according to the kinds of the operation. A multiple SIMD(Single Instruction Multiple Data) processor for multimedia data process includes a HC(Host Controller), a control unit, a program memory, an SIMD operation unit and a data bus. According to the host controller is the kinds of calculation, the control right of each control unit is assigned. According to the allocated control right, a first and N control units through the first delivers an instruction read from the program memory to the corresponding SIMD arithmetic unit.
Abstract translation: 提供用于处理用于操作的多媒体数据的SIMD处理器和使用其的操作方法，以通过根据操作的种类分配控制单元的控制权来提高多媒体数据的操作效率。 用于多媒体数据处理的多个SIMD（单指令多数据）处理器包括HC（主机控制器），控制单元，程序存储器，SIMD操作单元和数据总线。 根据主机控制器的种类计算，分配控制单元的控制权。 根据分配的控制权，通过第一个的第一和第N个控制单元将从程序存储器读取的指令传送到相应的SIMD算术单元。
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公开(公告)号：KR100900790B1
公开(公告)日：2009-06-02
申请号：KR1020070046833
申请日：2007-05-15
Applicant: 한국전자통신연구원
Abstract: 본 발명은 이진 신호의 가산, 감산 연산 및 논리연산을 처리하는 산술 및 논리 연산기, 이진 신호의 곱셈 연산을 처리하는 곱셈기, 이진 신호의 배열을 변경하는 시프터, 산술 및 논리 연산기, 곱셈기 및 시프터의 출력값 중 하나를 선택하는 제1 피연산자 선택기 및 제2 피연산자 선택기 및 제1 피연산자 선택기 및 제2 피연산자 선택기의 출력값을 더하는 덧셈기를 포함하는 재구성형 프로세서 연산기를 제공할 수 있다.
재구성형, 프로세서, 산술 및 연산 처리 장치, ALU(Arithmetic Logic Unit)-
Patent Agency Ranking
公开(公告)号：KR1020080052194A
公开(公告)日：2008-06-11
申请号：KR1020070046833
申请日：2007-05-15
Applicant: 한국전자통신연구원
Abstract: A method and an apparatus for operating a reconfigurable processor are provided to enhance operation performance and efficiency of the reconfigurable processor which is reconfigured to various applications and performs a massive operation. An apparatus for operating a reconfigurable processor includes an ALU(Arithmetic Logic Unit)(401), a multiplier(403), a shifter(405), the first operand selector(407), the second operand selector(409), an adder(415) and an accumulator(421). The ALU performs an arithmetic or logic operation by using inputted operands but does not have a final adder unlike a conventional one. The multiplier performs a multiplication operation without a final adder unlike a conventional one. The shifter receives the operand and shifts bits of the operand. The first operand selector selects one needed in an adder between an input signal received from the ALU, the multiplier and the shifter and a direct value directly inputted from a processor controller. The second operand selector selects one between the signal of the ALU and the adder and the signal fed back from the accumulator. The adder receives a signal selected from the first operand selector, the second operand selector and a carry input selector(411) and performs an addition operation. The accumulator temporarily stores an addition result value for performing an MAC(Multiply and Accumulate) operation frequently used in the processor.
Abstract translation: 提供了一种用于操作可重新配置的处理器的方法和装置，以增强可重配置处理器的操作性能和效率，该可重构处理器被重新配置为各种应用并执行大规模操作。 一种用于操作可重构处理器的装置，包括ALU（算术逻辑单元）（401），乘法器（403），移位器（405），第一操作数选择器（407），第二操作数选择器（409） 415）和蓄电池（421）。 ALU通过使用输入的操作数执行算术或逻辑运算，但不像传统操作数那样不具有最终的加法器。 乘法器执行乘法运算，而不需要最终的加法器，这与传统的加法器不同。 移位器接收操作数并移位操作数的位。 第一操作数选择器从ALU接收的输入信号，乘法器和移位器之间选择加法器中需要的一个，以及从处理器控制器直接输入的直接值。 第二个操作数选择器在ALU的信号和加法器的信号和从累加器反馈的信号之间选择一个。 加法器接收从第一操作数选择器，第二操作数选择器和进位输入选择器（411）中选择的信号，并执行相加操作。 累加器临时存储用于执行在处理器中频繁使用的MAC（乘法和累加）操作的相加结果值。
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公开(公告)号：KR101729976B1
公开(公告)日：2017-04-25
申请号：KR1020110055762
申请日：2011-06-09
Applicant: 한국전자통신연구원
CPC classification number: G06K9/6239 , G06K9/6269
Abstract: 본발명에따른영상인식장치는입력영상으로부터입력벡터를추출하는입력벡터추출부, 입력벡터를프로젝션벡터를사용하여압축벡터로변환하는압축벡터변환부, 훈련벡터를입력받고, 훈련벡터의폴딩연산을통해획득한프로젝션벡터를사용하여훈련파라미터를생성하는훈련파라미터생성부, 및압축벡터를훈련파라미터를사용한영상분류를통해영상인식데이터를출력하는영상분류부를포함한다.
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公开(公告)号：KR101725121B1
公开(公告)日：2017-04-12
申请号：KR1020110106863
申请日：2011-10-19
Applicant: 한국전자통신연구원
CPC classification number: G06K9/6228 , G06K9/6269 , G06N99/005
Abstract: 본발명은특징벡터분류장치및 방법에관한것이다. 본발명의실시예에의한특징벡터분류장치는초기조건설정부, 훈련벡터를입력받아상기초기조건설정부에서설정된값을통해오차및 가중치를계산하는변수계산부, 상기계산된오차및 가중치를입력받고, 상기계산된오차와오차문턱을비교하여재계산여부를결정하는루프결정부및 상기루프결정부로부터종료신호를입력받으면경계면을생성하는경계면생성부를포함한다. 따라서본 발명은높은분류성능을가지면서도적은연산만을요구하는특징벡터분류장치및 방법을제공한다.
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公开(公告)号：KR101706201B1
公开(公告)日：2017-02-15
申请号：KR1020100128379
申请日：2010-12-15
Applicant: 한국전자통신연구원
CPC classification number: G06F13/28
Abstract: 본발명은다이렉트메모리액세스컨트롤러및 그것의동작방법에관한것이다. 상기다이렉트메모리액세스컨트롤러는레지스터셋에구성된루프레지스터셋을통해채널별 루프전송을, 채널루프관리메모리장치에저장된데이터를통해전체채널에대한루프전송을수행한다. 상기다이렉트메모리액세스컨트롤러는전송할블럭데이터에대한전송정보를자체적으로변경하여다이렉트메모리액세스전송동작을수행할수 있다.
Abstract translation: 公开了具有第一和第二DMA通道的直接存储器访问（DMA）控制器的操作方法。 操作方法包括：基于第一DMA通道的循环信息和传送信息来迭代地执行第一DMA通道的DMA传送操作; 基于所述第二DMA通道的循环信息和传送信息迭代地执行所述第二DMA通道的DMA传送操作; 重新配置第一和第二DMA通道的传送和循环信息; 并且基于第一和第二DMA通道的重新配置的传输和循环信息，再次执行迭代地执行第一DMA通道的DMA传送操作和迭代地执行第一DMA通道的DMA传送操作。
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公开(公告)号：KR101697512B1
公开(公告)日：2017-01-19
申请号：KR1020110135208
申请日：2011-12-15
Applicant: 한국전자통신연구원
CPC classification number: G06T3/0068
Abstract: 본발명은영상정합장치및 방법에관한것이다. 본발명의실시예에의한영상정합장치는영상을입력받는영상입력부, 상기입력된영상으로부터호모그래피행렬을생성하는정합정보생성부및 상기호모그래피행렬을기초로영상을정합하는와핑부를포함하며, 상기정합정보생성부는상기입력된영상의피사체들에대한거리정보를생성하는거리정보생성기, 상기생성된거리정보를근사하는거리정보모델링기, 상기근사된거리정보에서겹침정보를생성하는겹침정보생성기, 상기겹침정보로부터매칭쌍을결정하는매칭쌍결정기및 상기매칭쌍으로부터호모그래피행렬을생성하는호모그래피행렬생성기를포함한다. 본발명에의한영상정합장치및 방법은감소된계산량을가지므로고속으로실시간영상정합이가능하다.
Abstract translation: 公开了一种图像注册装置，其包括接收图像的图像输入单元; 图像信息生成单元，其从输入图像生成单应性矩阵; 以及基于单应性矩阵来登记图像的翘曲单元。 所述登记信息生成部包括距离信息生成部，其生成与所述输入图像对象相对应的距离信息; 距离信息建模器近似所生成的距离信息; 重叠信息生成器，其从所述近似距离信息生成重叠信息; 匹配对确定器，其从所述重叠信息确定匹配对; 以及从匹配对生成单应性矩阵的单应性矩阵生成器。
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