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公开(公告)号：KR1020100073242A
公开(公告)日：2010-07-01
申请号：KR1020080131861
申请日：2008-12-23
Applicant: 한국전자통신연구원 , 광운대학교 산학협력단
CPC classification number: H04N19/129 , H03M7/42 , H04N19/42
Abstract: PURPOSE: A bit stream processor processing a variable length code codec is provided to support a multi-standard codec by using a syntax processor which controls a table storing a plurality of zigzag scan orders. CONSTITUTION: A syntax processor(170) outputs a run value and a level value by syntax-processing a bit stream. A zigzag table(190) stores a plurality of zigzag scan orders. A run-level processor(150) performs the run-level decoding by receiving the run value and the level value. The run-level processor stores the execution result according to the zigzag order corresponding to the codec of the bit stream among the zigzag scan orders. The syntax processor stores a new zigzag scan order in the zigzag table. The run-level processor is comprised of a hardwired logic. The syntax processor comprises a general microprocessor.
Abstract translation: 目的：提供处理可变长度代码编解码器的位流处理器，以通过使用控制存储多个之字形扫描顺序的表的语法处理器来支持多标准编解码器。 构成：语法处理器（170）通过语法处理位流来输出运行值和电平值。 之字形表（190）存储多个锯齿形扫描顺序。 运行级处理器（150）通过接收运行值和电平值来执行运行级解码。 运行级处理器根据在Z字形扫描顺序中与比特流的编解码器相对应的之字形顺序存储执行结果。 语法处理器在Z字形表中存储新的之字形扫描顺序。 运行级处理器由硬连线逻辑组成。 语法处理器包括通用微处理器。
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公开(公告)号：KR100960148B1
公开(公告)日：2010-05-27
申请号：KR1020080042497
申请日：2008-05-07
Applicant: 한국전자통신연구원
CPC classification number: G06F9/3001 , G06F9/30189 , G06F9/3802 , G06F9/3885
Abstract: 데이터 프로세싱 회로는, 동작 제어 신호 및 메모리 제어 신호를 출력하는 제어 유닛과, 각각이 상기 메모리 제어 신호에 응답해서 명령을 출력하는 복수의 프로그램 메모리들, 그리고 각각이 상기 동작 제어 신호에 응답해서 상기 복수의 프로그램 메모리들로부터의 명령들 중 어느 하나를 선택적으로 수행하는 연산기들을 포함하여 동작 환경에 따라서 유연하게 동작 모드 변환이 가능하다.
Abstract translation: 数据处理电路包括：控制单元，用于输出操作控制信号和存储器控制信号;多个程序存储器，每个用于响应于存储器控制信号输出命令; 以及一个操作单元，用于有选择地从多个程序存储器的程序存储器中执行任何一个指令。
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公开(公告)号：KR1020090116511A
公开(公告)日：2009-11-11
申请号：KR1020080042497
申请日：2008-05-07
Applicant: 한국전자통신연구원
CPC classification number: G06F9/3001 , G06F9/30189 , G06F9/3802 , G06F9/3885
Abstract: PURPOSE: A data processing circuit is provided to convert efficiently an operating mode according to the operating environment by implementing a multi-mode of a parallel processing. CONSTITUTION: A control unit(110) outputs the operating control signal and memory control signal. Program memories(121-123) output a command in response to the memory control signal. Computing units(131-133) respond to the operating control signal and selectively perform one command among the program memories. The operating control signal outputted from the control unit includes SIMD mode signal and memory selection control signal on SIMD(Single Instruction stream Multiple Data stream) mode.
Abstract translation: 目的：提供数据处理电路，通过实现并行处理的多模式，根据操作环境有效地转换操作模式。 构成：控制单元（110）输出操作控制信号和存储器控制信号。 程序存储器（121-123）响应于存储器控制信号输出命令。 计算单元（131-133）响应于操作控制信号，并且在程序存储器中选择性地执行一个命令。 从控制单元输出的操作控制信号包括SIMD（单指令流多数据流）模式下的SIMD模式信号和存储器选择控制信号。
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公开(公告)号：KR1020090065274A
公开(公告)日：2009-06-22
申请号：KR1020070132760
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: G06F15/78
Abstract: A reconfigurable SoC(System on Chip) system and a method of implementing the same are provided to perform dynamic reconfiguration by operating based on the automatic sensing of an IP necessary for the reconfiguration of an SoC. A flash memory(130) stores plural IPs(Internet Protocols), and an intrinsic code detecting unit(120) detects the intrinsic code of an IP called from a system software(110). A reconfigurable SoC(140) has a processor. The reconfigurable SoC unit configures an SoC by reading out an IP corresponding to the sensed intrinsic code.
Abstract translation: 提供了可重新配置的SoC（片上系统）系统及其实现方法，以通过基于对SoC的重新配置所需的IP的自动感测进行操作来执行动态重新配置。 闪存（130）存储多个IP（互联网协议），并且内部代码检测单元（120）检测从系统软件（110）调用的IP的固有代码。 可重新配置的SoC（140）具有处理器。 可重新配置的SoC单元通过读出对应于感测到的内在代码的IP来配置SoC。
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