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公开(公告)号：SG46200A1
公开(公告)日：1998-02-20
申请号：SG1996000481
申请日：1992-07-02
Applicant: IBM
Inventor： LUMELSKY LEON
Abstract: An image buffer is described for an XxY pixel display, which image buffer stores compressed image pixel data for a plurality of n x m matrices of pixels, each matrix represented by a pair of color codes and MASK having nm bit position, each positions mapping to a pixel in the matrix, a manifested bit value in a MASK bit position defining the color code assigned to a mapped pixel. The image buffer includes serial registers for feeding pixel color code values to a buffer serial output and multiplexers for providing n bit values from the MASK on n of its output lines. Gating circuitry, controlled by bit values on the output lines, are operative to gate either a first set of inputs or a second set of inputs into the shift registers. Control circuitry is provided for feeding a pair of color codes and the MASK bit values to the gating circuits and multiplexers, respectively, and for serially operating the serial shift registers in response to the gating of the inputs from the gating circuits.
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公开(公告)号：SG43717A1
公开(公告)日：1997-11-14
申请号：SG1996000134
申请日：1992-07-02
Applicant: IBM
Inventor： CHOI SUNG MIN , LUMELSKY LEON , PEEVERS ALAN WESLEY , PITTAS JOHN LOUIS
IPC: G09G5/06 , G06T3/00 , G06T11/20 , G09G5/14 , G09G5/36 , G09G5/395 , H04N5/265 , H04N5/272 , H04N5/262 , G09G1/16
Abstract: Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.
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公开(公告)号：DE69123883T2
公开(公告)日：1997-07-17
申请号：DE69123883
申请日：1991-05-15
Applicant: IBM
Inventor： LUMELSKY LEON
IPC: G06F3/153 , G09G5/00 , G09G5/36 , G09G5/39 , G09G5/391 , G09G5/393 , G09G5/395 , G09G5/397 , G09G5/399 , H04N5/262 , H04N5/44
Abstract: Image conversion method and apparatus that provides for (a) storing in a first memory a first image field; (b) storing in a second memory a second image field; (c) reading the first and the second memories; (d) simultaneously displaying on a display screen the first and the second image fields as a single image frame; and (e) while performing the step of reading the method includes a step of storing in a third memory a third image field. The first, second and third memories are provided as a frame buffer having a 3x3 memory block organization. For image fields numbered 1, 2, 3, 4, 5...n.. the system of the invention reads the image fields two at a time in accordance with a predetermined sequence given by: 1 and 2, 2 and 3, 3 and 4, 4 and 5, ... (n - 1) and n, n and (n + 1). A high resolution frame length is selected to be longer than or shorter than a television field period. The phase difference between the two is measured and circuitry alters the predetermined read-out sequence to ensure that a field memory to be read will not also be required for simultaneously storing a next television field.
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公开(公告)号：DE69211435T2
公开(公告)日：1996-12-05
申请号：DE69211435
申请日：1992-07-02
Applicant: IBM
Inventor： LUMELSKY LEON
Abstract: An image buffer is described for an XxY pixel display, which image buffer stores compressed image pixel data for a plurality of n x m matrices of pixels, each matrix represented by a pair of color codes and MASK having nm bit position, each positions mapping to a pixel in the matrix, a manifested bit value in a MASK bit position defining the color code assigned to a mapped pixel. The image buffer includes serial registers for feeding pixel color code values to a buffer serial output and multiplexers for providing n bit values from the MASK on n of its output lines. Gating circuitry, controlled by bit values on the output lines, are operative to gate either a first set of inputs or a second set of inputs into the shift registers. Control circuitry is provided for feeding a pair of color codes and the MASK bit values to the gating circuits and multiplexers, respectively, and for serially operating the serial shift registers in response to the gating of the inputs from the gating circuits.
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Patent Agency Ranking
公开(公告)号：DE69020753T2
公开(公告)日：1996-03-14
申请号：DE69020753
申请日：1990-02-21
Applicant: IBM
Inventor： LUMELSKY LEON , MCCABE DANIEL HELMUT , PEEVERS ALAN WESLEY
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公开(公告)号：DE69015536T2
公开(公告)日：1995-07-06
申请号：DE69015536
申请日：1990-06-05
Applicant: IBM
Inventor： LUMELSKY LEON , PEEVERS ALAN W , CHOI SUNG MIN
IPC: H04N5/66 , G06T3/40 , G09G5/00 , G09G5/02 , G09G5/14 , G09G5/36 , H04N1/393 , H04N5/262 , H04N7/01 , H04N3/22 , G06T3/60 , G09G1/00
Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor. According to a preferred embodiment of the invention the expansion circuit functions to modify the controi signals which controls the read-out of the frame buffer in a predetermined fashion without any additional video buffer storage means. In the simplest form of the invention the additional circuitry required comprises only two registers for holding the generated expansion patterns in the horizontal and vertical direction and two shift registers for receiving these patterns and processing same to alter the frame buffer clocks to achieve replication of predetermined lines and pixels as determined from the said expansion pattern.
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公开(公告)号：DE3852185D1
公开(公告)日：1995-01-12
申请号：DE3852185
申请日：1988-01-26
Applicant: IBM
Inventor： GUPTA SATISH , LUMELSKY LEON , SEGRE MARC
Abstract: A frame buffer is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. :p. The writing of individual pixels in this array is enabled by energising the write enable pins to each memory chip directly. The data wires in the memory organisation are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same. :p.The frame buffer includes a selectively energisable plane mask for disabling desired planes of accessed pixels. By sequentially controlling the output enables to the different rows of the addressed M by N array, the frame buffer can provide rapid access to N-1 rows after normally accessing the first one.
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公开(公告)号：DE3889136T2
公开(公告)日：1994-11-17
申请号：DE3889136
申请日：1988-01-26
Applicant: IBM
Inventor： GUPTA SATISH , LUMELSKY LEON , MANSFIELD ROBERT LOCKWOOD , ROMERO HECTOR GERARDO , SEGRE MARC , SPENCER ALEXANDER KOOS , ST CLAIR JOE CHRISTOPHER , WAGONER JAMES DONALD
Abstract: As the speed and capacity of graphics workstations and personal computers including graphics adapters increases, a display adapter which can be used either in such a high capacity stand alone graphics workstation or in conjunction with a large main frame host computer includes a first processor for managing adapter resources and controlling coordinate transformations; a system storage for storing instructions and data representing information to be displayed; a first-in, first-out input buffer for allowing asynchronous and overlapped communication between the graphics system and a host computer;a second processor for drawing vectors and manipulating areas to be displayed on the monitor;a frame buffer connected to the second processor for storing a bit map of data to be displayed; a colour palette connected to outputs of the frame buffer for providing appropriate colour signals to the monitor; and a hardware cursor circuit for controlling display of a cursor on the monitor.
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