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    Integrated memory has delay circuit for connection to control line to output signal delayed with respect to cell selection signal with capacitance for charging or discharging by current source
    54.
    发明专利
    Integrated memory has delay circuit for connection to control line to output signal delayed with respect to cell selection signal with capacitance for charging or discharging by current source 未知

    公开(公告)号：DE10056881A1

    公开(公告)日：2002-05-29

    申请号：DE10056881

    申请日：2000-11-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  KAISER ROBERT

    IPC: G11C8/08 ,  G11C8/10 ,  G11C8/00

    Abstract: The memory has a cell field with row lines for selecting memory cells and column lines for reading or writing data signals to/from cells, a row decoder, address lines connected to the row decoder, a control line connected to the row decoder and a delay circuit for connection to the control line to output a signal delayed with respect to a cell selection signal with a current source and a capacitance for charging/discharging by the current source. The memory has a memory cell field with row lines for selecting memory cells and column lines for reading or writing data signals to/from cells, a row decoder for activating row lines, address lines connected to the row decoder for transferring address signals, a control line for indicating the validity of the address signal connected to the row decoder and a delay circuit (8) for connection to the control line to output an output signal delayed with respect to a cell selection signal with a current source and a capacitance for charging or discharging by the current source.

    55.
    发明专利
    未知

    公开(公告)号：DE10004648C2

    公开(公告)日：2002-03-14

    申请号：DE10004648

    申请日：2000-02-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JOHNSON BRET A ,  KAISER ROBERT

    IPC: G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/407 ,  G11C7/00

    Abstract: An integrated semiconductor memory having memory cells (MC) for storing data signals (DQ), has a memory sense amplifier (2) with an input (21) for a data signal (DQ) of one of the memory cells (MC), and an output (23) for at least one output signal (RD0). A driver circuit (3) is connected to the output (23) of the memory sense amplifier (2). The driver circuit (3) can be activated or deactivated only by the output signal (RD0) of the memory sense amplifier (2). A signal line (4) is connected to the driver circuit (3), a precharging circuit (5) and to a memory circuit (6). A terminal (7) for a control signal (C) is connected to the memory sense amplifier (2), the precharging circuit (5) and the memory circuit (6). As result of a driver circuit (3) which has a relatively low level of circuit complexity, the space requirements are kept relatively small. In addition, high switching speeds are made possible during the reading operation.

    Integrated circuit for analysis of input signal characteristics has one port for first input signal, which adopts first and second state during first signal period and another port for second input signal
    58.
    发明专利
    Integrated circuit for analysis of input signal characteristics has one port for first input signal, which adopts first and second state during first signal period and another port for second input signal 未知

    公开(公告)号：DE102004059447A1

    公开(公告)日：2006-06-14

    申请号：DE102004059447

    申请日：2004-12-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAMBERGER FLORIAN ,  KAISER ROBERT

    IPC: G11C7/10 ,  G11C11/407

    Abstract: Integrated circuit has one port (T1) for first input signal (CLK), which adopts first and second state during first signal period and another port (T2) for second input signal (bCLK). First memory circuit (10) stores first state of second input signal and second memory circuit (20) stores the first state of second input signal. Input side (SHin) of first memory circuit is linked to port of second input signal and input side of second memory circuit is linked to port of second input signal. First memory circuit is designed such that input side of first memory circuit stored the first state of second input signal in it during delivery period of first state of second input signal. Second memory circuit is designed such that input side of second memory circuit stored the input state of second input signal in it during delivery period of second state of first input signal. Current evaluation circuit (40) for the generation of evaluating signal (AS) stored state (S1) of second input signal in first memory circuit. Current evaluation circuit is designed such that output side (A40) is generated by evaluating signal and state of second input signal is stored in first memory circuit and state (B1) of second input signal is stored in second memory circuit distinctively. Current evaluation circuit is designed such that output side is generated by evaluating signal and state of second input signal is stored in first memory circuit and state of second input signal is stored in second memory circuit, which is coinciding. An independent claim is also included for method of analysis of input signal characteristic of an integrated circuit.

    59.
    发明专利
    未知

    公开(公告)号：DE10117614B4

    公开(公告)日：2005-06-23

    申请号：DE10117614

    申请日：2001-04-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

    IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

    Abstract: A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a clock pulse with respect to the operating clock of the other, second memory bank. Partial data streams are combined at the output of the two memory banks to form a data stream with double the frequency.

    60.
    发明专利
    未知

    公开(公告)号：DE10115614C2

    公开(公告)日：2003-12-18

    申请号：DE10115614

    申请日：2001-03-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

    IPC: G11C5/14 ,  G11C29/12 ,  H01L23/58 ,  G11C29/00 ,  H01L21/66 ,  H01L23/525

    Abstract: A method for supplying current to a semiconductor chip, particularly to a semiconductor memory chip, in which, in a standby mode, the semiconductor chip is supplied with current from a standby current generator, and in which, in a normal operating mode, the semiconductor chip is supplied with current from a normal mode current generator. The standby current generator provides a smaller current than the normal mode current generator, and where, in a product development phase, the semiconductor chip is supplied with current from the standby current generator in a test mode. The semiconductor chip is additionally to be supplied with current from the normal mode current generator in the product development phase.

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