公开(公告)号：US20240006284A1

公开(公告)日：2024-01-04

申请号：US17855298

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Pietambaram ,  Benjamin Duong ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/16 ,  H01L23/49894 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L23/5386

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices. An example apparatus includes an electrically conductive layer, a dielectric layer, and an electrically nonconductive layer separating the dielectric layer from the conductive layer, the nonconductive layer having a first surface facing the conductive layer and a second surface facing the dielectric layer, the first surface having a first roughness, the second surface having a second roughness greater than the first roughness.

公开(公告)号：US20230387027A1

公开(公告)日：2023-11-30

申请号：US17752941

申请日：2022-05-25

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Haobo Chen

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/3128 ,  H01L24/16 ,  H01L25/0655 ,  H01L2221/68359 ,  H01L2224/16227

Abstract: A via structure for an embedded component and method for making same. The via structure includes a pillar of conductive material perpendicularly attached to a surface of a build-up dielectric layer. The surface and the pillar are conformally covered by a film layer. The film layer is conformally applied and retains a feature landscape profile. A dielectric layer is located on the film layer, the dielectric layer has an upper dielectric surface that is planar. The pillar has a top that is exposed at the upper dielectric surface. The film layer can act as a barrier to cracking because it is selected to have a higher hardness than the material making up the dielectric layer

公开(公告)号：US20230197661A1

公开(公告)日：2023-06-22

申请号：US17555401

申请日：2021-12-18

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Bai Nie ,  Haobo Chen ,  Jason M. Gamba

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L2224/0557 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2924/2075 ,  H01L2224/215 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2225/06513

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a first material layer on the first surface of the first die, the first material layer including silicon and nitrogen; a second material layer on the first material layer, the second material layer including a photoimageable dielectric; conductive vias through the first and second material layers, wherein respective ones of the conductive vias are electrically coupled to respective ones of the second conductive contacts on the first die; and a second die in a second layer, wherein the second layer on the first layer, and wherein the second die is electrically coupled to the second conductive contacts on the first die by the conductive vias.

公开(公告)号：US20210375746A1

公开(公告)日：2021-12-02

申请号：US16884452

申请日：2020-05-27

Applicant: INTEL CORPORATION

Inventor： Hongxia Feng ,  Jeremy Ecton ,  Aleksandar Aleksov ,  Haobo Chen ,  Xiaoying Guo ,  Brandon C. Marin ,  Zhiguo Qian ,  Daryl Purcell ,  Leonel Arana ,  Matthew Tingey

IPC: H01L23/522 ,  H01L23/66

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

公开(公告)号：US20210287979A1

公开(公告)日：2021-09-16

申请号：US16817309

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Henning Braunisch ,  Hiroki Tanaka ,  Haobo Chen

IPC: H01L23/498

Abstract: Embodiments may relate to a microelectronic package with an interconnect stack that includes a cavity therein. The cavity may include a dielectric material with a dielectric value less than 3.9. The microelectronic package may further include first and second conductive elements in the cavity, with the dielectric material positioned therebetween. Other embodiments may be described or claimed.