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    PROTOCOL ENGINE FOR PROCESSING DATA IN A WIRELESS TRANSMIT/RECEIVE UNIT
    54.
    发明专利
    PROTOCOL ENGINE FOR PROCESSING DATA IN A WIRELESS TRANSMIT/RECEIVE UNIT 未知

    公开(公告)号：CA2613426A1

    公开(公告)日：2007-01-11

    申请号：CA2613426

    申请日：2006-06-27

    Applicant: INTERDIGITAL TECH CORP

    Inventor： REZNIK ALEXANDER ,  GAZDA ROBERT G ,  HEPLER EDWARD L

    IPC: H04J11/00 ,  H04L49/901 ,  H04W88/02

    Abstract: A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re- formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer t he data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processed the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory.

    DATA-MOVER CONTROLLER WITH PLURAL REGISTERS FOR SUPPORTING CIPHERING OPERATIONS
    56.
    发明专利
    DATA-MOVER CONTROLLER WITH PLURAL REGISTERS FOR SUPPORTING CIPHERING OPERATIONS 未知

    公开(公告)号：CA2567818A1

    公开(公告)日：2005-12-08

    申请号：CA2567818

    申请日：2005-05-06

    Applicant: INTERDIGITAL TECH CORP

    Inventor： HEPLER EDWARD L ,  GAZDA ROBERT G

    IPC: H04L9/00 ,  G06F21/00 ,  H04L29/06

    Abstract: A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm “f8” or integrity cipher algorithm “f9”.

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