公开(公告)号：WO1981003402A1

公开(公告)日：1981-11-26

申请号：PCT/US1981000570

申请日：1981-04-29

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  SIEVERS K ,  MORTONSON R

IPC: H02J07/14

CPC classification number: G01R31/007 ,  G01R31/343 ,  H02J7/1461

Abstract: Detector (28) monitoring the voltage ripple in the rectified electrical output signal of an alternator (22) in a multiphase alternator battery charging system. A circuit monitors the undulating alternator output signal and produces a signal level in response. To correct the detector operation for various magnetic phenomena present in the alternator, a first circuit measures the rotational speed of the rotor and produces a proportional signal. A second circuit determines the excitation current supplied to the field coil. The measurement and determination are separately weighted and combined to form a corrected comparison threshold value. A variable threshold circuit combines the signal proportional to the rotational speed of the rotor and the determined field coil excitation current to produce a combined signal level. Comparison means compare the signal level from the monitored alternator output signal with the combined signal level and produce an output signal level indicative of the detection of a voltage ripple in excess of the combined signal level. The output signal is corrected for the effects of significant alternator performance characteristics.

Abstract translation: 检测器（28）监测多相交流发电机电池充电系统中交流发电机（22）的整流电输出信号中的电压纹波。 电路监视波动交流发电机输出信号并产生响应的信号电平。 为了校正交流发电机中存在的各种磁现象的检测器操作，第一电路测量转子的转速并产生比例信号。 第二电路确定提供给励磁线圈的励磁电流。 测量和确定被单独加权并组合以形成校正的比较阈值。 可变阈值电路将与转子的转速成比例的信号和确定的励磁线圈励磁电流组合以产生组合的信号电平。 比较装置将来自监测的交流发电机输出信号的信号电平与组合信号电平进行比较，并产生指示超过组合信号电平的电压纹波检测的输出信号电平。 对于显着的交流发电机性能特征的影响，输出信号被校正。

公开(公告)号：WO1981003401A1

公开(公告)日：1981-11-26

申请号：PCT/US1981000569

申请日：1981-04-29

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  SIEVERS K

IPC: H02J07/14

CPC classification number: H02J7/1461 ,  G01R31/007 ,  Y02T10/7005 ,  Y10S320/13

Abstract: In situ self-diagnostic automotive alternator battery charging system. Included are: a battery (74); voltage regulator (82) sensing battery voltage and generating an excitation signal; and an alternator (22) driven by a vehicle engine provide a rectified electrical signal to charge the battery in response to the excitation signal. Electronic circuit status detectors (84, 88, 90, 92, 94, 96, 98, 100), variously coupled to the battery, voltage regulator (82) and alternator (22), maintain a first logic state when a corresponding signal characteristic is within a predetermined range and a second logic state when the corresponding characteristic is outside the predetermined range. Combinatorial logic means (86, 102, 104) respond to a logic state sequence from the detectors to identify predetermined sequences of the logic states resulting in the identification of faults in the charging system. The logic means (104) also provides a warning to the operator of detection of a fault and a display of the location of the fault as occurring in one of the major components of the charging system.

Abstract translation: 原位自诊断汽车交流发电机电池充电系统。 包括：电池（74）; 电压调节器（82）感测电池电压并产生激励信号; 并且由车辆发动机驱动的交流发电机（22）提供整流的电信号，以响应于激励信号对电池充电。 各种耦合到电池，电压调节器（82）和交流发电机（22）的电子电路状态检测器（84,88,90,92,94,96,98,100）保持第一逻辑状态，当相应的信号特性为 在相应的特性在预定范围之外的预定范围内和第二逻辑状态。 组合逻辑装置（86,102,104）响应来自检测器的逻辑状态序列，以识别导致收费系统中故障识别的逻辑状态的预定序列。 逻辑装置（104）还向操作者提供警报，以检测故障并显示故障的位置，如在充电系统的主要部件之一中发生的。

公开(公告)号：WO1981003094A1

公开(公告)日：1981-10-29

申请号：PCT/US1981000375

申请日：1981-03-16

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  SHAW M ,  FREIMARK R

IPC: H03F03/04

CPC classification number: G01L9/045 ,  G01D3/036 ,  H03F1/302

Abstract: Amplifier circuit for temperature compensating the output voltage thereof with respect to undesirable temperature induced signals from a silicon pressure transducer (10) and/or from components of the amplifier itself. The amplifier includes a first operational amplifier (50) and a second operational amplifier (68). A first circuit connects the output terminal of the first operational amplifier through a summing node (66) to one input terminal (70) of the second amplifier. Output signals from the pressure transducer are applied between one input terminal (52) of the first operational amplifier and another input terminal (72) of the second amplifier. A temperature compensating circuit (116) is connected to the summing node for enabling the output voltage of the amplifier to be substantially independent of temperature. An initial offset voltage compensating circuit (80) is coupled to the summing node for adjusting the intercept of the pressure-to-output voltage transfer curve. The gain of the second operational amplifier determines the slope of the curve.

Abstract translation: 用于相对于来自硅压力传感器（10）和/或放大器本身的组件的不期望的温度感应信号来温度补偿其输出电压的放大器电路。 放大器包括第一运算放大器（50）和第二运算放大器（68）。 第一电路将第一运算放大器的输出端通过求和节点（66）连接到第二放大器的一个输入端（70）。 来自压力传感器的输出信号被施加在第一运算放大器的一个输入端（52）和第二放大器的另一个输入端（72）之间。 温度补偿电路（116）连接到求和节点，用于使放大器的输出电压基本上与温度无关。 初始偏移电压补偿电路（80）耦合到求和节点，用于调整压力 - 输出电压传递曲线的截距。 第二运算放大器的增益决定曲线的斜率。

公开(公告)号：WO1981002371A1

公开(公告)日：1981-08-20

申请号：PCT/US1981000010

申请日：1981-01-05

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  OOMS W

IPC: H03K21/36

CPC classification number: H03L7/193 ,  H03K23/667

Abstract: An improved frequency synthesizer suitable for use in mobile and portable radio applications using multiple dual modulus prescalers to achieve high frequency operation and low current drain. A first high speed prescaler (132) of limited size is used in conjunction with a second prescaler (170) to avoid the use of one large high speed prescaler to attain high frequency operation. Consequently, the frequency synthesizer can be constructed using only a minimum amount of high speed, high current drain logic thereby reducing cost and power consumption.

公开(公告)号：WO1981000654A1

公开(公告)日：1981-03-05

申请号：PCT/US1980000881

申请日：1980-07-14

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  KRUMIN D ,  TOTH R

IPC: H04B01/08

CPC classification number: H05K5/0086 ,  B29C45/14 ,  H04B1/086

Abstract: Housing for electronic apparatus (10), such as a radio or paging device, including an enclosure (20, 22) made of a suitable rigid material, which may be metal or plastic (26), with resilient material (34) on the outside surface thereof. The resilient material may be a urethane elastomer which is thermoplastic and can be applied to the rigid material by injection molding. The elastomer can completely cover the enclosure, including a movable control element (14) thereon, to provide a rugged shock absorbing and scuff and contaminant resistant housing for the apparatus therein.

Abstract translation: 电子设备（10）的外壳，例如无线电或寻呼设备，包括由合适的刚性材料制成的外壳（20,22），其可以是金属或塑料（26），弹性材料（34）在外部 表面。 弹性材料可以是热塑性的聚氨酯弹性体，并且可以通过注射成型施加到刚性材料上。 弹性体可以完全覆盖外壳，包括其上的可移动控制元件（14），以为其中的装置提供坚固的减震和抗磨损和抗污染外壳。

公开(公告)号：WO1981000332A1

公开(公告)日：1981-02-05

申请号：PCT/US1980000895

申请日：1980-07-07

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  DAVIS W

IPC: H03K23/30

CPC classification number: G11C19/28 ,  H01L27/0233 ,  H03K3/288

Abstract: A bistable circuit and shift register requiring less chip area and with greatly reduced current drain is realized with I sL logic gates. Each cell (28) of the register includes only four logic gates (10), connected as two binary R-S flip-flops, each gate consisting of a pair of merged PNP and NPN transistors. The two flip-flops are alternately energized by switching the current into the gate injectors in accordance with the phase of the clock signal. The use of fewer gates with simplified interconnections contribute to reduce chip area and current drain.

Abstract translation: 双通道电路和移位寄存器需要更少的芯片面积和大大减少的电流消耗是用I s s逻辑门来实现的。 寄存器的每个单元（28）仅包括四个逻辑门（10），连接为两个二进制R-S触发器，每个门由一对合并的PNP和NPN晶体管组成。 通过根据时钟信号的相位将电流切换到栅极注入器来交替地激励两个触发器。 使用具有简化互连的较少门有助于减少芯片面积和电流消耗。

公开(公告)号：WO1980002881A1

公开(公告)日：1980-12-24

申请号：PCT/US1980000713

申请日：1980-06-09

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  THOMPSON R

IPC: G06F13/00

CPC classification number: G11C16/105 ,  G11C5/066 ,  G11C16/102 ,  G11C16/32

Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), an EPROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and an input pin for providing a RESET signal or programming potential V u (23). An EPROM control register (53) in the CPU is loadable under the control of a computer program stored in an external memory (40). Responsive to a first bit in the EPROM control register an address buffer/latch (61) and a data latch (62) temporarily latch address and data information during a write operation to the EPROM. Responsive to a second bit in the EPROM control register the programming potential is applied to the EPROM for a predetermined time to program the data information into the EPROM at its associated address. The accuracy of the programming operation may be verified using the CPU under the control of the external computer program, to compare the address and data information programmed into the EPROM with the original source of such information.

Abstract translation: 单片机包括CPU（1），RAM（2），EPROM（3），定时器（4），串行I / O通信逻辑（5），四个I / O端口（11-14） 以及用于提供RESET信号或编程电位V u（23）的输入引脚。 在存储在外部存储器（40）中的计算机程序的控制下，CPU中的EPROM控制寄存器（53）可以被加载。 响应于EPROM控制寄存器中的第一位，地址缓冲器/锁存器（61）和数据锁存器（62）在写入操作期间将地址和数据信息临时锁存到EPROM。 响应于EPROM控制寄存器中的第二位，将编程电位施加到EPROM一段预定的时间，以将数据信息编程到其相关地址处的EPROM中。 可以使用在外部计算机程序控制下的CPU来验证编程操作的精度，将编程到EPROM中的地址和数据信息与此类信息的原始源进行比较。

公开(公告)号：WO1980002862A1

公开(公告)日：1980-12-24

申请号：PCT/US1980000682

申请日：1980-06-09

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  JAVERI R ,  PETRIE A

IPC: F02P05/08

CPC classification number: F02P3/0456

Abstract: Digital dwell circuitry (121) for a spark and dwell ignition control system (10) Maximum advance (15, 16) and reference (17, 18) sensors are utilized to produce pulse transitions (t u, t u) which determine positions of maximum and minimum possible advance for spark ignition with respect to the position of the engine crankshaft. For each maximum advance sensor pulse transition (t u) a main counter (41) starts a sequential running count of speed independent clock pulses (C u) wherein the maximum count obtained by the counter is related to engine crankshaft speed. The running and maximum counts of the main counter (41) are utilized by dwell circuitry (121) to determine the time (t u) prior to the next maximum advance pulse (t u) at which spark coil excitation should occur. The main counter running count also determines several inputs to a read only memory (ROM) circuit (48) whose output controls a rate multiplier (53). The rate multiplier (53) receives input clock signals (C2), provides selective frequency division for these clock signals in accordance with the ROM output, and the output of the rate multiplier is coupled to an accumulator means (80, 81, 82) whose accumulated count is utilized to determine the occurrence of spark ignition by terminating spark coil excitation.

Abstract translation: 用于火花和停留点火控制系统的数字驻留电路（121）（10）利用最大前进（15,16）和参考（17,18）传感器来产生脉冲过渡（t u，u u，u u u ），其确定关于发动机曲轴的位置的火花点火的最大和最小可能提前的位置。 对于每个最大提前传感器脉冲转换（t uA u），主计数器（41）开始速度无关时钟脉冲（C u）的顺序运行计数，其中由计数器获得的最大计数与发动机曲轴 速度。 主计数器（41）的运行和最大计数由驻留电路（121）利用来确定在下一个最大提前脉冲（t uA u）之前的时间（t uu w u） 应该发生 主计数器运行计数还确定几个输入到只读存储器（ROM）电路（48），其输出控制速率倍增器（53）。 速率倍增器（53）接收输入时钟信号（C2），根据ROM输出为这些时钟信号提供选择性分频，速率倍增器的输出耦合到累加器装置（80,81,82），该累加器装置 累积计数用于通过终止火花线圈激励来确定火花点火的发生。

公开(公告)号：WO1987001547A1

公开(公告)日：1987-03-12

申请号：PCT/GB1986000525

申请日：1986-09-04

Applicant: MOTOROLA INC ,  SMITH, Robert

Inventor： MOTOROLA INC

IPC: H04M03/00

CPC classification number: H04M3/005 ,  H04Q11/04

Abstract: A subscriber line card arrangement, in which each of eight subscriber lines is interfaced by a respective high voltage analog circuit, followed by a low voltage circuit for performing essential analog functions including over-sampled analog-to-digital and digital-to-analog conversion. A single CMOS digital signal processor (DSP) is multiplexed between each of the eight channels to perform digital signal processing of the telephone signals in each channel. Silicon usage for the high voltage functions is reduced as is the amount of bipolar analog circuitry. Digital hardware is saved by multiplexing the DSP. The invention is useful in central offices and PABX's.

公开(公告)号：WO1982004515A1

公开(公告)日：1982-12-23

申请号：PCT/GB1982000161

申请日：1982-05-28

Applicant: MOTOROLA INC ,  BEESLEY GRAHAM EDGAR

Inventor： MOTOROLA INC

IPC: H04L07/04

CPC classification number: H04B14/044 ,  H04L7/042 ,  H04L7/046

Abstract: Systeme de traitement de donnees du type dans lequel a lieu une transmission d'un format de code possedant une forme presentant une pluralite d'inversions 1011010 etc. a partir de laquelle il est souhaitable de maintenir la synchronisation de bits pour les donnees d'entree une fois que la synchronisation initiale est obtenue. Le systeme se caracterise en ce qu'apres qu'un premier mot de code de synchronisation est reconnu, au moins une partie de tout mot de code de synchronisation suivant est echantillonne au moins deux fois (ou trois fois) par bit et compare a la structure connue des bits d'un mot de code de synchronisation connu pour permettre a la structure de bit de s'adapter au mieux a la structure de bit connue afin d'etre acceptee par le systeme pour echantillonner les donnees d'entree. Le meilleur ajustement peut etre constitue par un total cumule ou par une somme des plus petites erreurs comparees a la structure.