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    Manufacturing self-aligned borderless contacts and local interconnections
    52.
    发明专利
    Manufacturing self-aligned borderless contacts and local interconnections 未知

    公开(公告)号：GB2335539A

    公开(公告)日：1999-09-22

    申请号：GB9805671

    申请日：1998-03-17

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI

    IPC: H01L21/60 ,  H01L21/768 ,  H01L21/336

    Abstract: Self-aligned, borderless contacts and local interconnections of semiconductor devices are manufactured in an integral process which is compatible with the LOGIC self-aligned titanium silicide (SALICIDE) and N+/P+ poly dual gate process modules. Active and local interconnect areas 9' and 9" are formed on a semiconductor substrate between isolation trenches 31, and gates are formed above each area. The gates consist of layers of oxide 32, polysilicon 33a,b, silicide 34a,b and nitride 35a,b and have side wall spacers 37a,b,c,d. Ions are implanted to from source/drain regions 36, before part of the gate above the interconnect area 9' is etched away. Silicide layers 42a,b,c are then formed in the source/drain regions before a nitride layer 44 and an inter-layer dielectric layer 43a are deposited. Openings are then etched in the layers 44,43a, and barrier layers 45 and tungsten plugs 46 are formed in the openings to connect the active and local interconnect areas with a conductive layer 47 to provide contacts and interconnections to and within the device.

    A planarization technique for dram cell capacitor electrode
    53.
    发明专利
    A planarization technique for dram cell capacitor electrode 未知

    公开(公告)号：SG67386A1

    公开(公告)日：1999-09-21

    申请号：SG1997001260

    申请日：1997-04-19

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

    IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

    Abstract: A method of forming a DRAM includes forming a transfer FET on a substrate, the FET having a gate on a gate oxide layer above the substrate and a first and second source/drain region in the substrate on either side of a channel region under the gate. The first and second source/drain regions are typically exposed or nearly exposed in a spacer etch process. A silicon nitride etch stop layer is deposited over the entire structure and then a thick layer of oxide is deposited on the device. Chemical mechanical polishing is performed to provide a planar surface on the thick oxide layer. An opening is formed through the thick layer of oxide above the first source/drain region, stopping at the etch stop layer. The etch stop layer is removed within the opening in the thick layer of oxide and the underlying thin oxide layer is etched. A capacitor electrode can then be formed in contact with the exposed portion of the first source/drain region. A similar self-aligned method can be used to form the bit line contact for the device using the etch stop layer as a stop for the bit line contact etch. Practice of the method provides a manufacturing method having improved reliability and ease of use, particularly when practiced for DRAM capacitors that incorporate high dielectric constant dielectrics. The materials preferred for use within such DRAM capacitors have smaller process margins and so particularly benefit from the improved structure and process.

    DRAM manufacture
    54.
    发明专利
    DRAM manufacture 未知

    公开(公告)号：NL1008071C2

    公开(公告)日：1999-07-21

    申请号：NL1008071

    申请日：1998-01-20

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI

    IPC: H01L21/8242 ,  H01L21/3205 ,  H01L21/768

    Abstract: Fabricating a DRAM device comprises: (a) forming a transistor (55) with a gate (53), a source/drain region (52) and a word line (54) on a silicon substrate (50); (b) covering the transistor with an oxide layer (56); (c) forming a contact opening (57) in the oxide layer to expose a surface of the source/drain region; (d) forming a conductive layer (58) in the contact opening and covering the oxide layer; (e) patterning the conductive layer to form at least one bottom electrode (59) which is coupled with the source/drain region (52) by way of the contact opening; (f) forming a dielectric layer (60) over a surface of the bottom electrode and the oxide layer; (g) covering the dielectric layer with a titanium nitride layer to form a top electrode (61); (h) forming a titanium layer (62) on the top electrode; and (i) forming an interlevel dielectric layer (63).

    Process for making an integrated circuit device with embedded DRAM
    57.
    发明专利
    Process for making an integrated circuit device with embedded DRAM 未知

    公开(公告)号：GB2331839A

    公开(公告)日：1999-06-02

    申请号：GB9725020

    申请日：1997-11-26

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： WU H J ,  SUN SHIH-WEI ,  CHEN JACOB ,  YEW TRI-RUNG

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: Transfer FETs 104 and wiring lines 106 are provided for the embedded DRAM circuits and FETs 120 are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions 142,144 of the logic FETs may be subjected to a salicide process at this initial phase and a thick planarized oxide layer 136 is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed, preferably using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias 146,148,150 are formed to expose each of the source/drain regions 138,140 of the DRAM transfer FETs and to expose select conductors within the logic circuits. A conductor layer 152 e.g. of titanium nitride is deposited over the device and within the various contact vias through the planarized oxide layer 136. A capacitor dielectric layer 154 e.g. of tantalum pentoxide is provided over the device and then the capacitor dielectric layer is selectively removed from the contact vias 148,150 that become bit line contacts and logic interconnects. A conductive layer e.g. of tungsten is deposited and patterned to provide upper capacitor electrodes 158 and to complete the bit line contacts 160 and logic interconnects 162. The tungsten layer also can provide bit line wiring. The ¢ V cc potential for the upper capacitor electrodes can be provided to the circuit using a level of interconnect wiring 180,182 also used by the logic circuits.

    Integrated circuit component which avoids DRAM integration problems and facilitates contact opening etching
    58.
    发明专利
    Integrated circuit component which avoids DRAM integration problems and facilitates contact opening etching 未知

    公开(公告)号：NL1007403C2

    公开(公告)日：1999-05-17

    申请号：NL1007403

    申请日：1997-10-30

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

    IPC: H01L21/8242

    Abstract: An IC component, with an embedded memory and logic circuits on a single substrate, is produced by forming a contact opening in a conformal protective layer (129), which covers transmission and logic FETs (104, 120), to expose a source or drain region (118) of one of the transmission FETs (104), forming a charge storage capacitor (130, 132, 134) connected to this source or drain region (118) and then removing the protective layer (129) at least from the logic circuit regions. Production of an integrated circuit component, which includes an embedded memory and logic circuits on a single substrate, comprises: (i) forming a substrate (100) with transmission FETs (104) in and on embedded DRAM regions and with logic FETs (120) in and on logic circuit regions; (ii) forming a conformal protective layer (129) over the FETs (104, 120), the layer having the same thickness over the gate electrodes and the source/drain regions (128) of the logic FETs (120); (iii) removing a portion of the protective layer (129) to form a contact opening which exposes a source or drain region (118) of one of the transmission FETs (104); (iv) forming a lower capacitor electrode (130) in contact with the source/drain region (118) of the transmission FET (104); (v) successively forming a capacitor dielectric layer (132) and an upper capacitor electrode (134) above the lower capacitor electrode (130) to form a charge storage capacitor for the transmission FET (104); and (vi) removing the protective layer (129) at least from the logic circuit regions. An Independent claim is also included for production of a similar integrated circuit component, in which the embedded memory is an embedded DRAM.

    Method of making a self-aligned silicide
    59.
    发明专利
    Method of making a self-aligned silicide 未知

    公开(公告)号：GB2328078A

    公开(公告)日：1999-02-10

    申请号：GB9716395

    申请日：1997-08-01

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08

    Abstract: A method of making a MOS device comprising a self-aligned silicide layer 31 and an impurity diffusion region 29 in a lower part of the source/drain regions 23a adjacent to an isolating region 24, includes over-etching (Figure 2B) the isolating regions 24 to expose the surface of the source/drain regions. Ion implantation (Figure 2C) at a large tilt angle increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window 34, resulting in a lowering of both contact resistance and sheet resistance.

    IC production with embedded DRAM circuits and logic circuits on single chip
    60.
    发明专利
    IC production with embedded DRAM circuits and logic circuits on single chip 未知

    公开(公告)号：DE19757490A1

    公开(公告)日：1999-01-28

    申请号：DE19757490

    申请日：1997-12-23

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： WU H J ,  SUN SHIH-WEI ,  CHEN JACOB ,  YEW TRI-RUNG

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: Production of an IC component, with embedded DRAM circuits and logic circuits on a single substrate, involves (a) producing transfer FETs (104) in and on embedded DRAM circuit regions of the substrate (100); (b) producing logic FETs (120) in and on the logic circuit regions of the substrate (100); (c) forming a first insulating layer (136) on the transfer FETs (104) and on the logic FET (120)s; (d) defining first and second openings (146, 148) in the first insulating layer to expose the source/drain regions (138, 140) of at least one of the transfer FETs (104) and defining a third opening (150) to expose at least one conductor (134) within the logic circuit; (e) producing a first conductive layer (152) on the first insulating layer and within the openings for contacting one of the source/drain regions of a transfer FET (104), the conductive layer not filling the first opening (146); (f) producing a capacitor dielectric layer and then a second conductive layer within the first opening (146); and (g) patterning the conductive layers for laterally delimiting the upper and lower electrodes of a charge storage capacitor of an embedded DRAM.

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