公开(公告)号：US10925172B1

公开(公告)日：2021-02-16

申请号：US16702478

申请日：2019-12-03

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tse-Wei Wang

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K1/03

Abstract: A carrier structure includes a carrier having at least one through hole penetrating the carrier and a build-up circuit layer located on the carrier and including at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on a first surface of the carrier and includes at least one first pad disposed relative to the through hole. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive vias penetrate the first dielectric layer and are electrically connected to the first and second circuit layers.

公开(公告)号：US10685922B2

公开(公告)日：2020-06-16

申请号：US16240806

申请日：2019-01-07

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  Tzyy-Jang Tseng ,  Ra-Min Tain

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US12243838B2

公开(公告)日：2025-03-04

申请号：US17567883

申请日：2022-01-04

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  John Hon-Shing Lau

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.

公开(公告)号：US12160953B2

公开(公告)日：2024-12-03

申请号：US17992933

申请日：2022-11-23

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

公开(公告)号：US20240248264A1

公开(公告)日：2024-07-25

申请号：US18623035

申请日：2024-04-01

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: G02B6/42 ,  G02B6/12 ,  H01L23/498 ,  H01L25/065

CPC classification number: G02B6/4206 ,  G02B6/12004 ,  G02B6/4293 ,  H01L23/49816 ,  H01L25/0652

Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

公开(公告)号：US20240237209A9

公开(公告)日：2024-07-11

申请号：US17986899

申请日：2022-11-15

Applicant: Unimicron Technology Corp.

Inventor： Ping-Tsung Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/114 ,  H05K1/024 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0195 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

公开(公告)号：US20240138063A1

公开(公告)日：2024-04-25

申请号：US17986899

申请日：2022-11-15

Applicant: Unimicron Technology Corp.

Inventor： Ping-Tsung Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/114 ,  H05K1/024 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0195 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

公开(公告)号：US20240138059A1

公开(公告)日：2024-04-25

申请号：US17992933

申请日：2022-11-23

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K1/11 ,  H05K3/4644 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

公开(公告)号：US11764120B2

公开(公告)日：2023-09-19

申请号：US17155094

申请日：2021-01-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Pei-Chi Chen ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/49827

Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.

公开(公告)号：US11665832B2

公开(公告)日：2023-05-30

申请号：US17234805

申请日：2021-04-20

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/20 ,  H05K3/36 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  H05K3/02

CPC classification number: H05K3/46 ,  H05K3/022 ,  H05K3/386 ,  H05K3/4038

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.