公开(公告)号：US20230012572A1

公开(公告)日：2023-01-19

申请号：US17384903

申请日：2021-07-26

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Tse-Wei Wang

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/46 ,  H05K3/42

Abstract: The invention discloses a circuit board enhancing structure and a manufacture method thereof. The method includes the following steps: providing a substrate; forming a first circuit on the substrate; forming a first dielectric layer enclosing the first circuit on the substrate; forming a first opening on the first dielectric layer; forming a first pattern photoresist layer on the first dielectric layer to divide a surface of the first dielectric layer as a first structure enhancing area and a second circuit area, wherein the first opening is disposed in the first structure enhancing area; forming a second circuit in the second circuit area and a first enhancing structure in the first opening, wherein the first enhancing structure protrudes from the first opening; removing the first pattern photoresist layer; and forming a second dielectric layer enclosing the second circuit and the first enhancing structure on the first dielectric layer.

公开(公告)号：US11690180B2

公开(公告)日：2023-06-27

申请号：US17147474

申请日：2021-01-13

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tse-Wei Wang

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/03 ,  H05K3/40

CPC classification number: H05K3/4644 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4007 ,  H05K3/4038 ,  H05K2201/0175

Abstract: A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.

公开(公告)号：US20230268256A1

公开(公告)日：2023-08-24

申请号：US17890279

申请日：2022-08-18

Applicant: Unimicron Technology Corp.

Inventor： Chin-Sheng Wang ,  Ra-Min Tain ,  Wen-Yu Lin ,  Tse-Wei Wang ,  Jun-Ho Chen ,  Guang-Hwa Ma

IPC: H01L23/498 ,  H01L23/66 ,  H01L23/13 ,  H01L23/552 ,  H01L21/48 ,  H05K1/14 ,  H05K1/11

CPC classification number: H01L23/49811 ,  H01L23/66 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/49833 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/145 ,  H05K1/113 ,  H05K1/144 ,  H01L23/49822 ,  H01L2223/6622 ,  H01L2223/6677 ,  H01L24/16

Abstract: An electronic package structure and manufacturing method thereof. The electronic package structure includes a circuit board, an interposer, a chip, a circuit structure, and a coaxial conductive element. The interposer is disposed on the circuit board. The interposer has a through groove. The chip is disposed in the through groove and located on the circuit board to electrically connect with the circuit board. The circuit structure is disposed on the interposer. The coaxial conductive element penetrates the interposer to electrically connect the circuit structure and the circuit board. The coaxial conductive element includes a first conductive structure, a second conductive structure, and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure.

公开(公告)号：US10802637B1

公开(公告)日：2020-10-13

申请号：US16509462

申请日：2019-07-11

Applicant: Unimicron Technology Corp.

Inventor： Tse-Wei Wang ,  Cheng-Ta Ko

IPC: G06F3/041 ,  H01L33/52 ,  H01L33/50 ,  H01L33/62

Abstract: A touch-sensing display panel includes a substrate, a first circuit layer, a LED chip, a second circuit layer, a blocking wall, a second wire, and a third wire. The first circuit layer is on the substrate, including at least one first electrode, and a first wire. The LED chip is on and electrically connected to the first electrode. The second circuit layer is on the first circuit layer, including a second electrode, a touch sensing line, and a touch driving line. The blocking wall, the second wire, and the third wire are on the second circuit layer. The second wire extends to an inner sidewall and a top surface of the blocking wall, and electrically connects to the touch sensing line. The third wire extends to an outer sidewall of the blocking wall, and electrically connects to the touch driving line.

公开(公告)号：US20230268257A1

公开(公告)日：2023-08-24

申请号：US17902902

申请日：2022-09-05

Applicant: Unimicron Technology Corp.

Inventor： Chin-Sheng Wang ,  Ra-Min Tain ,  Wen-Yu Lin ,  Tse-Wei Wang ,  Jun-Ho Chen ,  Guang-Hwa Ma

IPC: H01L23/498 ,  H01L23/66 ,  H01Q1/38 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L23/66 ,  H01Q1/38 ,  H01L23/49822 ,  H01L23/49833 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L24/16

Abstract: An electronic package structure and its manufacturing method are provided. The electronic package structure includes an interposer, a circuit board, a chip, and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element located in the interposer substrate. The interposer substrate includes a cavity. The coaxial conductive element includes a first conductive structure, a second conductive structure surrounding the first conductive structure, and a first insulation structure. The first insulation structure is disposed between the first and second conductive structures. The circuit board is disposed on a lower surface of the interposer substrate and electrically connected to the coaxial conductive element. The chip is disposed in the cavity and located on the circuit board, so as to be electrically connected to the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connected to the coaxial conductive element.

公开(公告)号：US20210136931A1

公开(公告)日：2021-05-06

申请号：US17147474

申请日：2021-01-13

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tse-Wei Wang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11 ,  H05K1/03

Abstract: A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.

公开(公告)号：US10925172B1

公开(公告)日：2021-02-16

申请号：US16702478

申请日：2019-12-03

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tse-Wei Wang

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K1/03

Abstract: A carrier structure includes a carrier having at least one through hole penetrating the carrier and a build-up circuit layer located on the carrier and including at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on a first surface of the carrier and includes at least one first pad disposed relative to the through hole. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive vias penetrate the first dielectric layer and are electrically connected to the first and second circuit layers.