公开(公告)号：US20170322520A1

公开(公告)日：2017-11-09

申请号：US15660514

申请日：2017-07-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ying WU ,  Robert Bogdan STASZEWSKI ,  Yihong MAO

IPC: G04F10/00 ,  H03M1/50 ,  H03K5/135

CPC classification number: G04F10/005 ,  H03H19/004 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/50 ,  H03M2201/4233

Abstract: A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

公开(公告)号：US09740175B2

公开(公告)日：2017-08-22

申请号：US15370796

申请日：2016-12-06

Applicant: Marvell World Trade Ltd.

Inventor： Olivier Burg ,  Haisong Wang ,  Xiang Gao

IPC: H03M1/50 ,  G04F10/00 ,  H03M1/00 ,  H04M1/50 ,  H03M1/12 ,  H03B21/02 ,  H03L7/089

CPC classification number: G04F10/005 ,  H03B21/02 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/18 ,  H03M1/00 ,  H03M1/12 ,  H03M1/50 ,  H03M7/3004 ,  H03M2201/4233 ,  H04M1/505

Abstract: A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.

公开(公告)号：US09673833B1

公开(公告)日：2017-06-06

申请号：US15196707

申请日：2016-06-29

Applicant: Silicon Laboratories Inc.

Inventor： William J. Anker ,  Timothy A. Monk ,  Rajesh Thirugnanam

IPC: H03M1/10 ,  H03K3/03 ,  H03M1/12 ,  H03M1/56 ,  H03M1/00

CPC classification number: H03M1/1023 ,  H03K3/0315 ,  H03M1/00 ,  H03M1/0624 ,  H03M1/12 ,  H03M1/56 ,  H03M1/60 ,  H03M2201/4233

Abstract: Two sets of information (phase and cycle count) that are created asynchronously in a voltage controlled oscillator based analog-to-digital converter. A third set of information is created that is a delayed cycle count. The three sets of information are used to determine the proper alignment of the phase and the cycle count.

公开(公告)号：US09104181B1

公开(公告)日：2015-08-11

申请号：US14690220

申请日：2015-04-17

Applicant: Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seongook Jung ,  Jung-Hyun Park ,  Kyung Ho Ryu ,  Dong Hun Jung

IPC: H03M1/50 ,  G04F10/00 ,  H03M1/08 ,  H03M1/12 ,  H03L7/089 ,  H03M1/00

CPC classification number: G04F10/005 ,  H03L7/0891 ,  H03L7/0895 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M2201/4233

Abstract: A time-to-digital converter includes a first gated ring oscillator, a second gated ring oscillator, a phase adjusting unit, and a digital converter unit. The first gated ring oscillator includes a plurality of first delay cells connected in a cyclic structure and operating in response to an enable signal. The second gated ring oscillator includes a plurality of second delay cells connected in a cyclic structure and operating in response to the enable signal. The phase adjusting unit adjusts a phase of a second circulation signal circulating in the second gated ring oscillator so as for the second circulation signal to have a predetermined phase difference with respect to a first circulation signal circulating in the first gated ring oscillator. The digital converter unit samples output signals of the first delay cells and the second delay cells to output a digital value corresponding to duration of the enable signal.

Abstract translation: 时 - 数转换器包括第一门控环形振荡器，第二门控环形振荡器，相位调整单元和数字转换器单元。 第一选通环形振荡器包括以循环结构连接并响应于使能信号而工作的多个第一延迟单元。 第二选通环形振荡器包括以循环结构连接并响应于使能信号而工作的多个第二延迟单元。 相位调整单元调节在第二选通环形振荡器中循环的第二循环信号的相位，使得第二循环信号相对于在第一选通环形振荡器中循环的第一循环信号具有预定的相位差。 数字转换器单元对第一延迟单元和第二延迟单元的输出信号进行采样，以输出对应于使能信号的持续时间的数字值。

公开(公告)号：US09092013B2

公开(公告)日：2015-07-28

申请号：US14029699

申请日：2013-09-17

Applicant: QUALCOMM Incorporated

Inventor： Hui William Song ,  Mohamed Hassan Abu-Rahma

IPC: H03M1/12 ,  G04F10/00 ,  H03M1/00 ,  H03K5/135 ,  H03L7/081 ,  H04M1/50 ,  H03H11/26

CPC classification number: G04F10/005 ,  H03H11/265 ,  H03K5/135 ,  H03L7/0814 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233 ,  H04M1/505

Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.

Abstract translation: 提供了具有改进的抗亚稳性的时间 - 数字转换器（TDC）。 TDC包括由起始信号选通的环形振荡器。 停止信号触发使用主从触发器捕获来自环形振荡器的相位信号的值。 来自触发器的两个主级的信号被逻辑地组合以产生使计数器计数的计数器时钟信号。 触发器和计数器的输出被编码以产生开始信号和停止信号的转变之间的时间的数字表示。 由于来自触发器的主级的信号被停止信号捕获（并停止切换），所以计数器时钟信号停止翻转，并且计数器停止计数。 这确保捕获的相位信号和计数器的值是一致的，并且避免可能发生的亚稳态误差。

公开(公告)号：US20150116139A1

公开(公告)日：2015-04-30

申请号：US14401566

申请日：2013-03-25

Applicant: Robert Bosch GmbH

Inventor： Thomas Wuchert ,  Matthias Kalisch

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/18 ,  H03M1/10

CPC classification number: H03M1/0626 ,  G01D3/08 ,  H03M1/0629 ,  H03M1/1095 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/183 ,  H03M2201/4233 ,  H04B1/40 ,  H04L5/0007 ,  H04L7/042 ,  H04L25/00 ,  H04L25/03038 ,  H04L27/2647

Abstract: A method for interference suppression of a sampling process includes sampling an analog signal with a sampling frequency f, and determining whether an interference amplitude is present. The method provides that if an interference amplitude is present, the sampling frequency f is increased or decreased, and the method begins again with the sampling of the analog signal with the increased or decreased sampling frequency. In addition, a device is described for carrying out the method.

Abstract translation: 一种采样过程的干扰抑制方法包括以采样频率f对模拟信号进行采样，并确定是否存在干扰幅度。 该方法提供如果存在干扰幅度，则采样频率f增加或减小，并且随着模拟信号采样频率的增加或减小，该方法再次开始。 此外，描述了用于执行该方法的设备。

公开(公告)号：US20140320329A1

公开(公告)日：2014-10-30

申请号：US14265148

申请日：2014-04-29

Applicant: PANASONIC CORPORATION

Inventor： Shiro DOSHO ,  Masao TAKAYAMA

IPC: G04F10/00 ,  H03M1/18

CPC classification number: G04F10/005 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/18 ,  H03M1/00 ,  H03M1/12 ,  H03M1/18 ,  H03M2201/4233

Abstract: An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter.

Abstract translation: 边沿检测器包括接收环形振荡器的相位信号的触发器，在输入信号的边缘定时取消触发器的复位状态的复位器，以及对触发器的输出信号执行逻辑运算的逻辑运算器， 翻牌 相位状态检测器基于触发器的输出信号来检测在输入信号的边缘定时处发生的环形振荡器的相位状态。 时间 - 数字转换器将输入信号和逻辑运算器的输出信号之间的边沿间隔转换为数字值。 在输入信号的边缘定时处，锁存器锁存计数环形振荡器的输出信号的周期数的计数器的值。 操作者根据锁存器，相位状态检测器和时间 - 数字转换器的输出信号计算接收信号的数字值。

公开(公告)号：US08866654B2

公开(公告)日：2014-10-21

申请号：US13091928

申请日：2011-04-21

Applicant: Gregory J. Mann ,  Gin-Chung Wang

Inventor： Gregory J. Mann ,  Gin-Chung Wang

IPC: H03M1/00 ,  G01T1/17 ,  H03M1/12

CPC classification number: G01T1/17 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233

Abstract: A method and electronic device for outputting time values and energy of an analog input signal by dynamically determining a plurality of threshold values, comparing, using a plurality of comparator circuits, the plurality of threshold values against the analog input signal, outputting, using at least one time to digital conversion circuit connected to each of the plurality of comparator circuits, a plurality of time values, each time value output when the analog input signal meets or exceeds a threshold value of the threshold values, filtering the analog input signal, performing, using an analog-to-digital conversion circuit, analog-to-digital conversion of the filtered analog input signal to generate a digital signal, and calculating, in response to receiving a trigger signal, an energy of the digital signal.

Abstract translation: 一种用于通过动态地确定多个阈值来输出模拟输入信号的时间值和能量的方法和电子装置，使用多个比较器电路比较多个阈值与模拟输入信号的比较，至少使用 连接到多个比较器电路中的每一个的一次数字转换电路，多个时间值，当模拟输入信号达到或超过阈值的阈值时输出每个时间值，对模拟输入信号进行滤波， 使用模数转换电路，对经过滤波的模拟输入信号进行模数转换以产生数字信号，以及响应于接收到触发信号计算数字信号的能量。

公开(公告)号：US20140159930A1

公开(公告)日：2014-06-12

申请号：US14097451

申请日：2013-12-05

Applicant: MediaTek Inc.

Inventor： Chen-Yen HO ,  Hung-Chieh TSAI ,  Yu-Hsin LIN

IPC: H03M3/00

CPC classification number: H03M3/32 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/452 ,  H03M2201/4233

Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands.

Abstract translation: 提供Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器包括多级环路滤波器和量化器。 多级环路滤波器接收模拟输入信号，并根据模拟输入信号产生积分输出信号。 量化器耦合到多级环路滤波器。 量化器接收积分输出信号并量化积分输出信号以产生数字输出信号。 Σ-Δ调制器的不同前馈路径可用于不同的频带。

公开(公告)号：US4381499A

公开(公告)日：1983-04-26

申请号：US318887

申请日：1981-11-06

Applicant: Holger Struthoff

Inventor： Holger Struthoff

IPC: H03M1/78 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3136 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/814 ,  H03M2201/931

Abstract: A monolithic integrable R-2R resistor network comprises a number of series resistors connected to a terminal resistor; and a plurality of 2R resistor units each capable of being switched by two electronic switches either to ground or to another reference point, a different plurality of 2R resistor units being coupled to the nodes between each of the series resistors, to the node between the terminal resistor and the last resistor of the series resistors and to the node ahead of the first resistor of the series resistors. To compensate for the effects of the variations of the switch resistances caused during manufacture by process parameter fluctuations upon the accuracy of a D/A converter, a switch structure is inserted at each of the nodes which, with respect to the two electronic switches, is of the same kind, and which is permanently in an electrically conducting state. Preferably, there are used insulated-gate field-effect transistors and insulated-gate field-effect transistor structures, the identical electrodes of which, for example, the source electrodes, are directly connected to each of the nodes.

Abstract translation: 单片可积分R-2R电阻网络包括连接到端子电阻器的多个串联电阻器; 以及多个2R电阻单元，每个能够被两个电子开关切换到接地或另一个参考点，不同的多个2R电阻单元耦合到每个串联电阻之间的节点到端子之间的节点 电阻器和串联电阻器的最后一个电阻器，并连接到串联电阻器的第一个电阻器前面的节点。 为了补偿由于工艺参数波动而产生的开关电阻的变化对D / A转换器的精度的影响，在每个节点处插入开关结构，相对于两个电子开关 并且永久地处于导电状态。 优选地，使用绝缘栅场效应晶体管和绝缘栅场效应晶体管结构，其相同的电极例如源电极直接连接到每个节点。