公开(公告)号：US4381499A

公开(公告)日：1983-04-26

申请号：US318887

申请日：1981-11-06

Applicant: Holger Struthoff

Inventor： Holger Struthoff

IPC: H03M1/78 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3136 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/814 ,  H03M2201/931

Abstract: A monolithic integrable R-2R resistor network comprises a number of series resistors connected to a terminal resistor; and a plurality of 2R resistor units each capable of being switched by two electronic switches either to ground or to another reference point, a different plurality of 2R resistor units being coupled to the nodes between each of the series resistors, to the node between the terminal resistor and the last resistor of the series resistors and to the node ahead of the first resistor of the series resistors. To compensate for the effects of the variations of the switch resistances caused during manufacture by process parameter fluctuations upon the accuracy of a D/A converter, a switch structure is inserted at each of the nodes which, with respect to the two electronic switches, is of the same kind, and which is permanently in an electrically conducting state. Preferably, there are used insulated-gate field-effect transistors and insulated-gate field-effect transistor structures, the identical electrodes of which, for example, the source electrodes, are directly connected to each of the nodes.

Abstract translation: 单片可积分R-2R电阻网络包括连接到端子电阻器的多个串联电阻器; 以及多个2R电阻单元，每个能够被两个电子开关切换到接地或另一个参考点，不同的多个2R电阻单元耦合到每个串联电阻之间的节点到端子之间的节点 电阻器和串联电阻器的最后一个电阻器，并连接到串联电阻器的第一个电阻器前面的节点。 为了补偿由于工艺参数波动而产生的开关电阻的变化对D / A转换器的精度的影响，在每个节点处插入开关结构，相对于两个电子开关 并且永久地处于导电状态。 优选地，使用绝缘栅场效应晶体管和绝缘栅场效应晶体管结构，其相同的电极例如源电极直接连接到每个节点。

公开(公告)号：US4568912A

公开(公告)日：1986-02-04

申请号：US475406

申请日：1983-03-15

Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka

Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka

IPC: H03M1/00 ,  H04B12/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/162 ,  H03M2201/196 ,  H03M2201/198 ,  H03M2201/3115 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/415 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/532 ,  H03M2201/534 ,  H03M2201/648 ,  H03M2201/838

Abstract: In a data compression system, a digital signal comprising a series of digital samples and a sampling datum associated with each digital sample is received by a decoder. The sampling datum indicates the sampling interval of the associated digital sample. The decoder includes a microcomputer for storing the digital signal into a memory (M2) and reading each digital sample and the associated sampling datum. The digital sample is divided by the sampling datum to derive a quotient which indicates the slope of the signal to be recovered. The quotient is integrated by an integrator (6b) to provide interpolation between successive sampling points, so that the original signal is approximated by a plurality of line segments.

Abstract translation: 在数据压缩系统中，由解码器接收包括一系列数字样本和与每个数字样本相关联的采样数据的数字信号。 采样数据表示相关数字采样的采样间隔。 解码器包括用于将数字信号存储到存储器（M2）中并读取每个数字样本和相关联的采样数据的微型计算机。 数字样本被采样数据除以导出指示要恢复的信号的斜率的商。 积分器（6b）对商进行积分，以在连续采样点之间提供内插，使原始信号由多个线段近似。

公开(公告)号：US4349777A

公开(公告)日：1982-09-14

申请号：US204929

申请日：1980-11-07

Applicant: Masakazu Mitamura

Inventor： Masakazu Mitamura

IPC: G01R1/28 ,  G05F1/56 ,  H03M1/00 ,  G01R27/14 ,  G05F1/58 ,  G05F1/613

CPC classification number: G05F1/561 ,  H03M1/00 ,  H03M2201/02 ,  H03M2201/14 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4266 ,  H03M2201/60 ,  H03M2201/6121 ,  H03M2201/814

Abstract: A plurality of metal resistance elements and a metal resistance element for compensation use are formed on a common substrate and placed under the same temperature condition. A reference current is applied to the metal resistance element for compensation use to yield an auxiliary reference voltage. A plurality of switches are individually connected in series to the reference metal resistance elements and the auxiliary reference voltage is provided to the series circuits to selectively control the switches, thereby obtaining various currents.

Abstract translation: 在公共基板上形成多个金属电阻元件和用于补偿的金属电阻元件，并置于相同的温度条件下。 将参考电流施加到用于补偿使用的金属电阻元件以产生辅助参考电压。 多个开关分别与参考金属电阻元件串联连接，并且辅助参考电压被提供给串联电路以选择性地控制开关，从而获得各种电流。

公开(公告)号：US4338590A

公开(公告)日：1982-07-06

申请号：US110135

申请日：1980-01-07

Applicant: Joseph J. Connolly, Jr. ,  James B. Cecil

Inventor： Joseph J. Connolly, Jr. ,  James B. Cecil

IPC: H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3136 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/6121 ,  H03M2201/63 ,  H03M2201/814

Abstract: A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.

Abstract translation: 一个多级电阻梯形网络，使用额外的级来修剪阻抗差异。 所有的阶段都是相互联系的。 名义上，目前在每个阶段都分成两半。 响应于逻辑控制信号，一半的电流被门控在总线上，而另一半的电流被传递到下一个后续阶段。 由于各种处理限制，包括每个级的电阻器与它们的标称值略有不同，这反过来扰乱了当前的划分。 为了补偿这个额外的电流分级级与梯子的最后阶段串联连接。 来自这些附加级的电流除了通常耦合到其上的电流之外还响应于逻辑信号而选择性地耦合到总线上。

公开(公告)号：KR101879331B1

公开(公告)日：2018-07-18

申请号：KR1020170029313

申请日：2017-03-08

Applicant: 충북대학교 산학협력단

Inventor： 양병도 ,  김태우 ,  우기찬 ,  황선광 ,  김미정

IPC: H03M1/78

CPC classification number: H03M1/785 ,  H03M2201/3168 ,  H03M2201/814

Abstract: 본발명은이중출력용폴디드저항열디지털아날로그변환기에관한것으로서, 동일한저항값을갖는 2개의저항들이제1기준전압(V)과제2기준전압(V) 사이에직렬연결되어있는저항열(R)과, N/2의상위비트를출력하는워드라인디코더(Word line decoder)와, N/2의하위비트를출력하는비트라인디코더(Bit line decoder)와, 워드라인디코더의상위비트에대응하는각 출력단에접속되어스위칭되며, 저항열의해당전압값(V)을출력하는 2개의워드라인스위치(WL-S)와, 비트라인디코더의하위비트에대응하는각 출력단에접속되어스위칭되며, 하위비트에대응하는해당전압값(V)을출력하는 N 개의비트라인스위치(BL-S)와, 워드라인디코더의상위비트에대응하는각 출력단에접속되어스위칭되며, 각라인간이웃전압값(V)을출력하는 N 개의워드라인더미스위치(WL-DS)와, 비트라인디코더의하위비트에대응하는각 출력단에접속되어스위칭되며, 하위비트에대응하는해당이웃전압값(V)을전달하는 N 개의비트라인더미스위치(BL-DS)와, 비트라인스위치(BL-S) 및비트라인더미스위치(BL-DS)가일측단자가접속되고, 자신의출력단이타측단자에접속되는출력버퍼(Output buffer)를포함한다. 본발명에따르면, 고해상도를구현하면서도 R-DAC의스위치개수를최소화함으로써, R-DAC의칩 면적을감소시킬수 있다. 데이터구동부(Data Driver) IC칩면적에대부분은 R-DAC가차지하고있으므로, R-DAC의면적을줄임으로써데이터구동부 IC칩의크기감소및 원가절감을달성할수 있다. 또한, 스위치의수가줄어들면스위치가가지고있는기생저항, 캐패시터가감소해 R-DAC 동작속도가빨라져고속처리가가능하게된다.