公开(公告)号：US4381499A

公开(公告)日：1983-04-26

申请号：US318887

申请日：1981-11-06

Applicant: Holger Struthoff

Inventor： Holger Struthoff

IPC: H03M1/78 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3136 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/814 ,  H03M2201/931

Abstract: A monolithic integrable R-2R resistor network comprises a number of series resistors connected to a terminal resistor; and a plurality of 2R resistor units each capable of being switched by two electronic switches either to ground or to another reference point, a different plurality of 2R resistor units being coupled to the nodes between each of the series resistors, to the node between the terminal resistor and the last resistor of the series resistors and to the node ahead of the first resistor of the series resistors. To compensate for the effects of the variations of the switch resistances caused during manufacture by process parameter fluctuations upon the accuracy of a D/A converter, a switch structure is inserted at each of the nodes which, with respect to the two electronic switches, is of the same kind, and which is permanently in an electrically conducting state. Preferably, there are used insulated-gate field-effect transistors and insulated-gate field-effect transistor structures, the identical electrodes of which, for example, the source electrodes, are directly connected to each of the nodes.

Abstract translation: 单片可积分R-2R电阻网络包括连接到端子电阻器的多个串联电阻器; 以及多个2R电阻单元，每个能够被两个电子开关切换到接地或另一个参考点，不同的多个2R电阻单元耦合到每个串联电阻之间的节点到端子之间的节点 电阻器和串联电阻器的最后一个电阻器，并连接到串联电阻器的第一个电阻器前面的节点。 为了补偿由于工艺参数波动而产生的开关电阻的变化对D / A转换器的精度的影响，在每个节点处插入开关结构，相对于两个电子开关 并且永久地处于导电状态。 优选地，使用绝缘栅场效应晶体管和绝缘栅场效应晶体管结构，其相同的电极例如源电极直接连接到每个节点。

公开(公告)号：KR1020040058462A

公开(公告)日：2004-07-05

申请号：KR1020020084681

申请日：2002-12-27

Applicant: (주) 유엘에스

Inventor： 한건호

IPC: H03M1/06

CPC classification number: H03M1/06 ,  H03M2201/639 ,  H03M2201/931

Abstract: PURPOSE: A method and an apparatus for removing an error of an A/D converter are provided to simplify a structure of a circuit by using only an A/D converter. CONSTITUTION: A signal having an arbitrary frequency is generated by using an oscillator. A process for sampling and holding a waveform signal is performed in an oscillating process. An original signal is added to the signal after the sampling process and the holding process are performed. A voltage signal of the adding process is converted to a digital signal by using an ADC1. The voltage signal is converted to the digital signal by using an ADC2. A subtraction process is performed to obtain a difference between the digital signals.

Abstract translation: 目的：提供用于消除A / D转换器的误差的方法和装置，以通过仅使用A / D转换器来简化电路的结构。 构成：使用振荡器产生具有任意频率的信号。 在振荡处理中进行采样和保持波形信号的处理。 在采样处理之后将原始信号添加到信号并进行保持处理。 通过使用ADC1将加法处理的电压信号转换为数字信号。 电压信号通过使用ADC2转换为数字信号。 执行减法处理以获得数字信号之间的差异。

公开(公告)号：KR1020000019781A

公开(公告)日：2000-04-15

申请号：KR1019980038051

申请日：1998-09-15

Applicant: 삼성전자주식회사

Inventor： 이종화

IPC: H03M1/66

CPC classification number: H03M1/14 ,  H03M1/06 ,  H03M2201/6372 ,  H03M2201/931

Abstract: PURPOSE: A multiplying digital to-analog converter is provided to reduce a nonlinear characteristic generated owing to a mismatch of a capacitor array. CONSTITUTION: A multiplying digital-to-analog converter comprises a first reference terminal(pVref) supplied with a first reference voltage and a second reference terminal(nVref) supplied with a second reference voltage. A first capacitor array has first 2¬N unit capacitors(PC1-PC15) each corresponding to all bits of a first digital data inputted from a previous analog-to-digital converter and two fixed capacitors(PCfb1,PCfb2). A first select part has 2¬N switches(PS1-PS15) which connect one ends of the first unit capacitors and the first and second reference terminals in response to the first digital data. A second capacitor array has first 2¬N unit capacitors(nC1-nC15) each corresponding to all bits of a second digital data inputted from a previous analog-to-digital converter and two fixed capacitors(nCfb1,nCfb2). A second select part has 2¬N switches(NS1-NS15) which connect one ends of the second unit capacitors and the first and second reference terminals in response to the second digital data. An operational amplifier(OP) has a first input terminal coupled to the other ends of the first unit capacitors and a second input terminal coupled to the other ends of the second unit capacitors, and amplifies a difference between a digitized value of an external analog input signal and the analog signal.

Abstract translation: 目的：提供一个乘法数模转换器，以减少由于电容阵列不匹配而产生的非线性特性。 构成：乘法数模转换器包括提供有第一参考电压的第一参考端（pVref）和提供有第二参考电压的第二参考端（nVref）。 第一电容器阵列具有分别对应于从先前的模数转换器和两个固定电容器（PCfb1，PCfb2）输入的第一数字数据的所有位的第一2N单位电容器（PC1-PC15）。 第一选择部分具有响应于第一数字数据连接第一单元电容器的一端和第一和第二参考端子的2N开关（PS1-PS15）。 第二电容器阵列具有分别对应于从先前的模数转换器输入的第二数字数据和两个固定电容器（nCfb1，nCfb2）的所有位的第一2N单位电容器（nC1-nC15）。 第二选择部分具有响应于第二数字数据连接第二单位电容器和第一和第二参考端子的一端的2N开关（NS1-NS15）。 运算放大器（OP）具有耦合到第一单位电容器的另一端的第一输入端和耦合到第二单元电容器的另一端的第二输入端，并且放大外部模拟输入的数字化值 信号和模拟信号。

公开(公告)号：KR20100093214A

公开(公告)日：2010-08-25

申请号：KR20090012304

申请日：2009-02-16

Applicant: PUSAN NAT UNIV IND COOP FOUND

Inventor： NAM IL KU ,  LEE HYUNG SU ,  SEO SHIN HYOUK ,  CHOI JAE YI

IPC: H03M1/12

CPC classification number: H03M1/068 ,  H03M1/66 ,  H03M2201/8132 ,  H03M2201/931

Abstract: PURPOSE: A differential digital-to-analog converter using the complementary characteristic is provided to reduce unnecessary power consumption and whole system size by omitting a secondary circuit forming a differential phase clock. CONSTITUTION: A current supplying unit(100) includes one current source. The current supplying unit supplies a current corresponding to the output of a digital-to-analog converter by forming a p-type metal-oxide-semiconductor transistor with a current mirror. A current distributing unit(200) distributes a current from the current supplying unit into a plurality of distributed currents. A switching unit(300) controls the flow of the distributed currents. An impedance buffering unit(400) minimizes a current variation according to the switching operation of a switching unit. A voltage outputting unit(500) generates an outputting voltage by adding distributed currents.

Abstract translation: 目的：提供使用互补特性的差分数模转换器，通过省略形成差分相位时钟的次级电路来减少不必要的功耗和整个系统尺寸。 构成：电流供应单元（100）包括一个电流源。 电流供给单元通过形成具有电流镜的p型金属氧化物半导体晶体管来提供与数 - 模转换器的输出相对应的电流。 电流分配单元（200）将来自电流供应单元的电流分配到多个分布电流中。 开关单元（300）控制分布电流的流动。 阻抗缓冲单元（400）根据切换单元的切换操作使电流变化最小化。 电压输出单元（500）通过增加分布电流产生输出电压。

公开(公告)号：KR1020040099883A

公开(公告)日：2004-12-02

申请号：KR1020030032013

申请日：2003-05-20

Applicant: 학교법인 정석인하학원

Inventor： 윤광섭 ,  조현호

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/0863 ,  H03M2201/644 ,  H03M2201/814 ,  H03M2201/931

Abstract: PURPOSE: A deglitch circuit for improving performance of a digital/analog converter to execute a high-speed data transmission/reception operation is provided to improve the frequency capacity by minimizing the glitch energy. CONSTITUTION: A first PMOS transistor(M1) includes a gate for receiving a positive input signal and is turned on or off according to a logical state of the positive input signal. A first NMOS transistor(M3) includes a drain connected to a drain of the first PMOS transistor, a gate for receiving the positive input signal, and is turned on or off according to the logical state of the positive input signal. A third NMOS transistor(M5) includes a drain connected to a source of the first PMOS transistor, a gate for receiving the positive input signal, and is turned on or off according to the logical state of the positive input signal. A second PMOS transistor(M2) includes a gate for receiving a negative input signal and is turned on or off according to a logical state of the negative input signal. A second NMOS transistor(M4) includes a drain connected to a drain of the second PMOS transistor, a gate for receiving the negative input signal, and is turned on or off according to the local state of the negative input signal. A fourth NMOS transistor(M6) includes a drain connected to a source of the second PMOS transistor, a gate for receiving the negative input signal, and is turned on or off according to the local state of the negative input signal.

Abstract translation: 目的：提供一种用于提高数字/模拟转换器执行高速数据发送/接收操作性能的去电泳电路，通过最小化故障能量来提高频率容量。 构成：第一PMOS晶体管（M1）包括用于接收正输入信号的栅极，并根据正输入信号的逻辑状态导通或截止。 第一NMOS晶体管（M3）包括连接到第一PMOS晶体管的漏极的漏极，用于接收正输入信号的栅极，并且根据正输入信号的逻辑状态导通或截止。 第三NMOS晶体管（M5）包括连接到第一PMOS晶体管的源极的漏极，用于接收正输入信号的栅极，并且根据正输入信号的逻辑状态导通或截止。 第二PMOS晶体管（M2）包括用于接收负输入信号的栅极，并根据负输入信号的逻辑状态导通或截止。 第二NMOS晶体管（M4）包括连接到第二PMOS晶体管的漏极的漏极，用于接收负输入信号的栅极，并且根据负输入信号的本地状态导通或截止。 第四NMOS晶体管（M6）包括连接到第二PMOS晶体管的源极的漏极，用于接收负输入信号的栅极，并且根据负输入信号的本地状态导通或截止。