Abstract:
A disk unit-integrated display capable of increase in conveyance efficiency and reduce in conveyance cost of a disk unit, a holding member and a first circuit board unitized with each other can be obtained. This disk unit-integrated display (1) includes the disk unit (7) having a drive portion (73), the holding member (5) for supporting the disk unit (7), the first circuit board (6) arranged between the disk unit (7) and the holding member (5) and having an opening (6a) at a position corresponding to the drive portion (73) of the disk unit (7).
Abstract:
Das Keramik-Substrat (13) ist auf einer ersten Seite einer zum Modul gehörenden, Schaltungsstrukturen aufweisenden Leiterplatte (12) mittels eines flexiblen Klebers (2) befestigt und mittels Bondverbindungen (11) an die Schaltungsstrukturen kontaktiert, und die Anschlußelemente sind durch auf der Rückseite der Leiterplatte (12) angebrachte, annähernd kugelförmige Lotballungen (10) gebildet, die über Durchkontaktierungen mit den Schaltungsstrukturen auf der ersten Seite der Leiterplatte (12) verbunden sind.
Abstract:
Wireless interconnects are shown on flexible cables for communication between computing platforms. One example has an integrated circuit chip, a package substrate to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components, a cable on the package substrate coupled to the integrated circuit chip at one end, a radio chip on the cable coupled to the cable at the other end, the radio chip to modulate data over a carrier and to transmit the modulated data, and a waveguide transition coupled to a dielectric waveguide to receive the transmitted modulated data from the radio and to couple it into the waveguide, the waveguide to carry the modulated data to an external component.
Abstract:
A straddle mount connector (110) for connecting a daughter card (114) to a circuit board (112) comprises a dielectric housing (170) extending along a longitudinal axis (C). The housing has a straddle mount side (140) with a longitudinally extending mounting slot (180) that is configured to receive a mounting edge of the circuit board. The housing has a daughter card side (150) with a longitudinally extending mating slot (210) that is configured to receive a mating edge of the daughter card. The daughter card (114) can be inserted in the mating slot (210) at an acute insertion angle (α) with respect to a plane of the circuit board (112) and rotated to a fully mated position wherein the daughter card (114) is substantially coplanar with the circuit board (112).
Abstract:
The invention relates to a backplane for an electronic mounting rack having a basic backplane (1) with a plurality of contact strips, wherein a clearance, into which at least one additional backplane (3) can be inserted, is provided on the basic backplane (1).
Abstract:
A system for providing dual 10 GB uplinks in the front side of a single rack unit switch that stacks two MSA X2 I/O devices in a limited space. In one embodiment the two X2 I/O devices are mounted on opposite sides of a single circuit board positioned above the motherboard.
Abstract translation:在单个机架单元交换机的前侧提供双10 GB上行链路的系统,可在有限的空间中堆叠两个MSA X2 I / O设备。 在一个实施例中,两个X2 I / O设备安装在位于主板上方的单个电路板的相对侧上。
Abstract:
IC device assemblies including a power delivery bus board that is mounted to a primary PCB (i.e., motherboard) that further hosts a power-sink device and a power-source device. The bus board, as a secondary PCB, may be surface-mounted on a back side of the primary PCB opposite the power source and sink devices, which are mounted on the front side of the primary PCB. The bus board need only be dimensioned so as to bridge a length between first and second back-side regions of the primary PCB that are further coupled to a portion of the front-side pads employed by the power-sink device. The secondary PCB may be purpose-built for conveying power between the source and sink devices, and include, for example, short, wide traces, that may be formed from multiple heavyweight metallization layers.