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    Package for integrated circuit chips
    57.
    发明公开
    Package for integrated circuit chips 失效
    集成电路芯片封装

    公开(公告)号：EP0575806A3

    公开(公告)日：1994-03-16

    申请号：EP93109124.3

    申请日：1993-06-07

    Applicant: International Business Machines Corporation

    Inventor： Cipolla, Thomas Mario ,  Coteus, Paul William ,  Damianakis, Ioannis ,  Johnson, Glen Walden ,  Matthew, Linda Carolyn ,  Mok, Lawrence Shungwei ,  Ledermann, Peter Gerard

    IPC: H01L25/065

    CPC classification number: H05K3/363 ,  H01L24/01 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2225/06551 ,  H01L2225/06596 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/326 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/366 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09172 ,  H05K2201/09909 ,  H05K2201/10484 ,  H05K2201/1059 ,  H05K2201/10681 ,  H05K2201/10984 ,  H01L2924/00

    Abstract: This invention relates to three dimensional packaging of integrated circuit chips (306) into stacks to form cube structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate (300) having a plurality of conductors (316) one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures (318) can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contains solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate (302) surface or the pin-like structures can be adapted for insertion into apertures (320) in a second substrate. The second substrate provides a means for electrically interconnecting a plurality of these cubes. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cube.

    Abstract translation: 本发明涉及将集成电路芯片（306）三维封装成叠层以形成立方体结构。 在堆叠中的相邻芯片之间布置电互连装置，该电互连装置是具有多个导体（316）的第一衬底（300），所述多个导体的一端电连接到芯片接触位置并且另一端延伸到一个 以形成多个针状电互连组件。 针状结构（318）可以由第一衬底的突起形成，第一衬底在其至少一侧上具有从该侧延伸的导电体。 可选地，针状结构可以由从第一衬底的边缘的两侧悬伸的导体形成，从两侧对应的导体与第一衬底厚度对准并间隔开。 该空间包含焊料并形成焊料负载针状结构。 针状结构可以直接焊接到第二衬底（302）表面上的导体，或者针状结构可以适于插入第二衬底中的孔（320）中。 第二衬底提供用于电互连多个这些立方体的装置。 优选地，第一和第二基板是电路化的柔性聚合物膜。 第二衬底设置在诸如PC板之类的第三衬底上，其间具有弹性材料，其允许散热器被挤压成与立方体的相对侧紧密接触。

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