公开(公告)号：JPH07221780A

公开(公告)日：1995-08-18

申请号：JP27114094

申请日：1994-11-04

Applicant: ADVANCED MICRO DEVICES INC

Inventor： MASHIYUU JIEEMUZU FUITSUSHIYAA ,  GUREN GIBUSON ,  TOOMASU JIEFUAASON RUNARUDEYUU ,  JIEFUERII DOUWAAKU

IPC: G06F13/00 ,  G06F13/12 ,  H04L12/56 ,  H04L12/40 ,  H04L12/02

Abstract: PURPOSE: To accelerate the reception speed of a data packet from a network. CONSTITUTION: The system for ensuring the operation of an 'Ethernet' controller 22 so that the waiting time of a bus and the use of a central processing unit CPU are optimized in a network environment at the time of receiving the data packet is provided. A system prepares for the reception and the transmission of the data packet, from the 'Ethernet' controller during the waiting time of the network by effectively using plural buffer memories #1, #2 and #3 and a driver and by using the bus in connection to the controller 22. Thus, the whole performance of the network improves.

公开(公告)号：JPH07211811A

公开(公告)日：1995-08-11

申请号：JP30604394

申请日：1994-12-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： ROBAATO BII RICHIYAATO ,  SHIYAMU JII GAAGU ,  FUEI WAN

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a method for manufacturing a monolithic integrated circuit comprising a flash EPROM device. CONSTITUTION: An array 12 and a self-alignment source region in a redundancy select area 20 are, for opening a self-alignment source region and also for direct implantation of phosphorous of a small dose to a silicon substrate bellow it, provided with a single mask. A careful control and removal, thereafter, of the residue in an etched region through wet-etching is helpful for an implantation edge to be anisotropically controlled and separated with sure for lateral diffusion/drive-in thereafter. Thus, the flash EPROM device of a plurality of transistors in the array and the redundancy select area is process-controlled, thus significant reduction is provided in threshold skewing.

公开(公告)号：JPH07202707A

公开(公告)日：1995-08-04

申请号：JP31635194

申请日：1994-12-20

Applicant: ADVANCED MICRO DEVICES INC

Inventor： KAARIN DOURUU KEIBURAA

IPC: H03M3/02

Abstract: PURPOSE: To provide a method for cascading two secondary sigma-delta modulators. CONSTITUTION: A method includes a step for sending an input to a quantizer 24 of a 1st stage to a 2nd state. Actually this input is the difference between the output of a 1st second-order loop and the quantization noise of a 1st modulater 18. The method further includes a step for eliminating the quantization noise outputted from the 1st loop and also eliminating an output of the 1st loop from a final output yout .

公开(公告)号：JPH07202653A

公开(公告)日：1995-08-04

申请号：JP24002994

申请日：1994-10-04

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BIN GUUO ,  AASAA HIYU

IPC: H03K5/13 ,  H03K19/0175

Abstract: PURPOSE: To eliminate the need for noise filtration and to attain accurate delay resolution by selectively delaying pulses during the operation of a common drain of a pair of CMOS field effect transistors(FETs). CONSTITUTION: A parallel variable resistor Ron and variable capacitors Con , Coff are substituted for a parallel n-channel MOS gate circuit connected between a node (mid) and a negative power supply VSS. Although a response at the trailing edge of an input step signal (fti) is delayed for a slight fixed time by an output step signal (fto), the delay does not depend upon a resistor Ron and a capacitor Con and is controlled by a dispersion type capacitor CD. A response at the leading edge of the signal (fti) depends upon the resistor Ron and a capacitor Con . When the resistor Ron is set to a maximum value, a delay value is maximized. When the resistor Ron is set to ten steps e.g. an incremental delay difference between respective steps becomes smaller than a nominal delay value and respective incremental time delay values are made equal. Thereby a controllable time delay value smaller than the delay of an inverter of one step can be obtained.

公开(公告)号：JPH07200399A

公开(公告)日：1995-08-04

申请号：JP30451494

申请日：1994-12-08

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIBITSUDO BII UITSUTO

IPC: G06F12/08

Abstract: PURPOSE: To improve the performance of a set associative cache at a 1st level. CONSTITUTION: A microprocessor 10 includes a microprocessor core 15 placed on a semiconductor die and a set associative 1st level cache 30. A substitute cache 60 is placed on the same die and connected to the cache 30. In a 1st level cache miss mode, the 1st level entry is disused and stored in the cache 60. When the 1st level cache miss occurs, the cache 60 is checked. If the cache 60 has a hit, the hit entry is sent to the cache 30 and stored there. If the cache misses occur at both caches 30 and 60, a main memory access is started to fetch the desired entry. Then the fetched desired entry is sent to the cache 30 and stored there.

公开(公告)号：JPH07200093A

公开(公告)日：1995-08-04

申请号：JP29654494

申请日：1994-11-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： RITA EMU OBURAIEN

IPC: G06F1/04 ,  G06F1/32

Abstract: PURPOSE: To provide the power managing device of a computer system in which the supply of a power to a system oscillator can be controlled, and power consumption can be reduced. CONSTITUTION: An output signal from a power managing device 110 is applied, and when a computer system 100 is in a power saved and stopped state, an outside system oscillator which generates a system clock signal is turned off, and when this computer system is resumed, and it is in a ready state, this outside system oscillator is turned on. A counter is provided, and the latency of the output signal is controlled when the power managing device inputs and outputs the stopped state. This latency generates a time when a microprocessor clock and/or the other clock signals related with the system oscillator are turned into an operation stopped state before the oscillator is turned into the operation stopped state, and a time when the oscillator is stabilized before the clock signals are resumed. As a result, the power consumption of the computer system can be reduced, and the proper clock generation for this computer system can be maintained.

公开(公告)号：JPH07193057A

公开(公告)日：1995-07-28

申请号：JP29419994

申请日：1994-11-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SABUHATSUSHIYU GUPUTA ,  SUUZAN CHIEN ,  ANJIERA HIYUI

IPC: C23F4/00 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522

Abstract: PURPOSE: To enable via holes and openings with high aspect ratio to be formed in SiOx without deeply etching by using high pressure CHF3 and N2 , and high flow rate He plasma. CONSTITUTION: A lower electrode 21 of Al is supported by a plasma reaction apparatus housing 23, and a wafer 24 is clamped on the electrode 21 by a clamp 22. The electrodes 20 and 21 are positioned with a gap narrower than 1.5 cm, reactive gas flow containing CHF3 and N2 , is put into a sealed region, and RF power P with frequency of the order of 400 kHz is applied to the electrodes. Further, the plasma is cooled by inelastic collision, which causes high flow rate of He gas with low mass to mix with the reaction gas. However, the flow rate of He gas is greater than 96% of the whole mass flow. The wafer is processed by cooling He gas in the back face of the wafer which is performed under pressure via a duct 26 which passes He gas through a control device 25 to a space 30 below the wafer 24.

公开(公告)号：JPH07182163A

公开(公告)日：1995-07-21

申请号：JP26243794

申请日：1994-10-26

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIBITSUDO BII UITSUTO ,  MAIKERU DEI GODAADO

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/455

Abstract: PURPOSE: To provide the method and device which easily improve the performance of a CISC processor. CONSTITUTION: A super-scalar CISC processor 100 having a RISC super-scalar core 110 includes an instruction cache 104, a byte queue 106, and an instruction decoder 108. This decoder 108 includes a logic conversion route, a memory conversion route, and a common conversion route for conversion of a CISC instruction to RISC similar operation ROP in each issue position. An ROP multiplexer sends an x86 instruction from the byte queue 106 to conversion routes, and a selection circuit collects ROP information from proper conversion routes, and a shared circuit processes ROP information from the selection circuit for resources to be shared. An ROP type and op code information are issued from the instruction decoder to the RISC core.

公开(公告)号：JPH07154345A

公开(公告)日：1995-06-16

申请号：JP15204894

申请日：1994-07-04

Applicant: ADVANCED MICRO DEVICES INC

Inventor： MAAKU RUEDOUTOUKE

IPC: H03M1/38 ,  H03M1/46 ,  H04B17/00

Abstract: PURPOSE: To obtain perfect asynchronous implementation of a successive approximation algorithm by transmitting the intensity of received approximate radio frequency signals to a D/A converter and the output of a comparator to a state machine. CONSTITUTION: A received signal intensity indicating(RSSI) A/D converter 10 is constituted of a control block 12, a digital block 14, and an analog block 16 and the block 14 transmits an appropriate approximate value to the D/A converter of the analog block 16. The output of the D/A converter is impressed upon the comparator of the block 16. The comparator compares the output of the D/A converter with an RSSI signal and a state machine in the digital block 14 is adjusted so that approximation can be corrected appropriately based on the compared result of the comparator. This cycle is repeated at each of a prescribed number of bits and the final result is obtained.

公开(公告)号：JPH07153537A

公开(公告)日：1995-06-16

申请号：JP20366794

申请日：1994-08-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： REIMONDO ESU DEYUREI

IPC: H01L23/498 ,  H01R12/70 ,  H01R27/00 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K3/36 ,  H05K7/10 ,  H01R9/09 ,  H01R23/68

Abstract: PURPOSE: To appropriately correct an electric signal transmitted between a first element and a second element by providing a mutual connecting member having a plurality of first and second contacts and an electric signal changing element having an electric signal changing circuit. CONSTITUTION: A device 10 is interposed between a first element 12 and a second element 14. A mutual connecting member 22 disposed in the device 10 includes a plurality of first contacts 24 and second contacts 26, wherein the contacts 24 are supported on a first face 28 and the contacts 26 are supported on a second face 30. The contacts 24, 26 are parallel to each other, are arranged at narrow intervals, and engage with the elements 12, 14, respectively. An electric signal changing element 32 disposed in the device 10 includes an electric circuit for changing an electric signal transmitted between the elements 14, 12. The elements 32 are mutually connected between at least part of the contact 24 and at least part of the contact 26. Consequently, the electric signal transmitted between the elements 14 and 12 can be changed appropriately.