公开(公告)号：EP2005467A4

公开(公告)日：2011-05-18

申请号：EP07709446

申请日：2007-01-31

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD ,  BAUER TOMAS ,  EBEFORS THORBJOERN

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

公开(公告)号：EP1962679A4

公开(公告)日：2011-04-13

申请号：EP06824640

申请日：2006-12-14

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD ,  EBEFORS THORBJOERN ,  CORMAN THIERRY

IPC: A61B5/042 ,  A61B5/151 ,  A61B5/153 ,  A61M5/158 ,  A61M25/06 ,  A61M37/00 ,  A61N1/18 ,  G01N33/483

CPC classification number: A61M37/0015 ,  A61B5/053 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150984 ,  A61M2037/003 ,  A61M2037/0046 ,  A61M2037/0053 ,  A61N1/0502 ,  A61N1/0551 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/00014

公开(公告)号：EP1962679A2

公开(公告)日：2008-09-03

申请号：EP06824640.4

申请日：2006-12-14

Applicant: Silex Microsystems AB

Inventor： KÄLVESTEN, Edvard ,  EBEFORS, Thorbjörn ,  CORMAN, Thierry

IPC: A61B5/042 ,  A61B5/151 ,  A61B5/153 ,  A61M25/06 ,  A61M37/00 ,  A61M5/158 ,  A61N1/18 ,  G01N33/483

CPC classification number: A61M37/0015 ,  A61B5/053 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150984 ,  A61M2037/003 ,  A61M2037/0046 ,  A61M2037/0053 ,  A61N1/0502 ,  A61N1/0551 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/00014

Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.

公开(公告)号：SE2351074A1

公开(公告)日：2025-03-15

申请号：SE2351074

申请日：2023-09-14

Applicant: SILEX MICROSYSTEMS AB

Inventor： SANDIN ANDREAS ,  HELD LUCAS ,  SVEDIN NIKLAS

IPC: H01L21/3065 ,  H01L21/768 ,  H01L23/48

Abstract: The present invention relates to a semiconductor device ( 100) that prevents sidewall profile damages during etch, preferably a deep reactive ion etching, of a through silicon via, TSV, ( 150) through a Si layer (110) of a stack in the semiconductor device (100). This is achieved by, in a via-last process, using a first conductive material (130, 130’, 130”) embedded in an insulating layer (120) of the stack as an etch stop. The even TSV sidewall profile thus obtained simplifies subsequent metallization of the TSV using physical vapor deposition, PVD. The present invention further includes a method of manufacturing such a semiconductor device (100). The improved, more reliable, metallization obtained using the inventive semiconductor device (100) leads to improved conductivity of the TSV (150), as well as a less costly and complex manufacturing process with improved yield.

公开(公告)号：SE538018C2

公开(公告)日：2016-02-09

申请号：SE1151268

申请日：2011-12-22

Applicant: SILEX MICROSYSTEMS AB

Inventor： KÄLVESTEN EDVARD ,  EBEFORS THORBJÖRN ,  ERIKSSON ANDERS

IPC: H01L21/762 ,  A61M37/00 ,  B81C1/00 ,  H01L21/768

公开(公告)号：SE537584C2

公开(公告)日：2015-06-30

申请号：SE1151201

申请日：2011-12-15

Applicant: SILEX MICROSYSTEMS AB

Inventor： SVEDIN NIKLAS ,  EBEFORS THORBJÖRN

IPC: B81C1/00

公开(公告)号：SE537406C2

公开(公告)日：2015-04-21

申请号：SE1250672

申请日：2012-06-21

Applicant: SILEX MICROSYSTEMS AB

Inventor： ÅGREN PETER

IPC: B81B7/02 ,  B81B5/00 ,  G02B26/08 ,  H01L21/30 ,  H01L21/768 ,  H01L23/522

公开(公告)号：SE1151268A1

公开(公告)日：2013-06-23

申请号：SE1151268

申请日：2011-12-22

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD ,  EBEFORS THORBJOERN ,  ERIKSSON ANDERS

IPC: H01L21/762 ,  A61M37/00 ,  B81C1/00 ,  H01L21/768

公开(公告)号：SE1151201A1

公开(公告)日：2013-06-16

申请号：SE1151201

申请日：2011-12-15

Applicant: SILEX MICROSYSTEMS AB

Inventor： SVEDIN NIKLAS ,  EBEFORS THORBJOERN

IPC: B81C1/00

公开(公告)号：SE536058C2

公开(公告)日：2013-04-16

申请号：SE1150429

申请日：2011-05-12

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD

IPC: B01L3/00 ,  C03B23/24 ,  G01N21/05 ,  G01N35/08