公开(公告)号：US20230058180A1

公开(公告)日：2023-02-23

申请号：US17505686

申请日：2021-10-20

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Yu-Shen Chen ,  Chung-Yu Lan

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/32 ,  H05K3/02 ,  H05K3/42

Abstract: A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

公开(公告)号：US11562972B2

公开(公告)日：2023-01-24

申请号：US17463559

申请日：2021-09-01

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Yu-Chi Shen ,  Tzyy-Jang Tseng ,  Chen-Hua Cheng ,  Pei-Wei Wang

IPC: H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L23/00 ,  H01Q1/22

Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

公开(公告)号：US11516910B1

公开(公告)日：2022-11-29

申请号：US17371114

申请日：2021-07-09

Applicant: Unimicron Technology Corp.

Inventor： Chia-Yu Peng ,  John Hon-Shing Lau ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: H01R12/52 ,  H05K1/02 ,  H05K1/11 ,  H05K3/24 ,  H05K3/06 ,  H05K3/40

Abstract: A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.

公开(公告)号：US20220367307A1

公开(公告)日：2022-11-17

申请号：US17875443

申请日：2022-07-28

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.

公开(公告)号：US11477886B2

公开(公告)日：2022-10-18

申请号：US17367419

申请日：2021-07-05

Applicant: Unimicron Technology Corp.

Inventor： Yunn-Tzu Yu ,  Ching-Ho Hsieh ,  Wang-Hsiang Tsai

IPC: H05K1/14 ,  H05K1/11

Abstract: A circuit board structure includes a body, multiple first pads, a conductive assembly, multiple first engaging components, and multiple second engaging components. The body includes a first portion and a second portion integrally formed. A first surface of the first portion directly contacts a second surface of the second portion. A first region of the first surface protrudes from the second portion, and a second region of the second surface protrudes from the first portion. The first pads and the first engaging components are disposed on the first portion of the body and located in the first region of the first surface. The conductive assembly and the second engaging components are disposed on the second portion of the body and located in the second region of the second portion. The first pads are located between the first engaging components, and the conductive assembly is located between the second engaging components.

公开(公告)号：US11462452B2

公开(公告)日：2022-10-04

申请号：US17156626

申请日：2021-01-24

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L21/78

Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.

公开(公告)号：US11445596B2

公开(公告)日：2022-09-13

申请号：US17153856

申请日：2021-01-20

Applicant: Unimicron Technology Corp.

Inventor： Chin-Sheng Wang ,  Pei-Chang Huang

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/00

Abstract: A circuit board includes an open substrate and a heat dissipation block. The open substrate includes a substrate body, an opening and at least one first fixing portion and at least one second fixing portion. The substrate body has a top surface and a bottom surface. The opening is in the substrate body and has a first sidewall and a second sidewall opposite to the first sidewall. The first fixing portion and the second fixing portion extends from the substrate body toward the opening, in which the first fixing portion and the second fixing portion are respectively protruded from the first sidewall and the second sidewall. The heat dissipation block is directly clamped between the first fixing portion and the second fixing portion.

公开(公告)号：US20220287182A1

公开(公告)日：2022-09-08

申请号：US17826178

申请日：2022-05-27

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Yu-Hua Chen ,  Chun-Hsien Chien ,  Wen-Liang Yeh ,  Ra-Min Tain

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46

Abstract: An embedded component structure includes a board, an electronic component, and a dielectric material layer. The board has a through cavity. The board includes an insulating core layer and a conductive member. The insulating core layer has a first surface and a second surface opposite thereto. The through cavity penetrates the insulating core layer. The conductive member extends from a portion of the first surface along a portion of the side wall of the through cavity to a portion of the second surface. The electronic component includes an electrode. The electronic component is disposed in the through cavity. The dielectric material layer is at least filled in the through cavity. The connection circuit layer covers and contacts the conductive member and the electrode. A manufacturing method of an embedded component structure is also provided.

公开(公告)号：US20220285255A1

公开(公告)日：2022-09-08

申请号：US17232109

申请日：2021-04-15

Applicant: Unimicron Technology Corp.

Inventor： Yan-Jia Peng ,  Kuo-Ching Chen ,  Pu-Ju Lin

IPC: H01L23/498 ,  H05K3/46 ,  H01L23/12 ,  H01L23/528 ,  H01L23/532 ,  H01L23/16 ,  H01L23/00 ,  H01L21/50 ,  H01L21/768

Abstract: A method of fabricating a wiring board with an embedded interposer substrate includes preparing a main substrate, forming a recess on the main substrate, placing an interposer substrate into the recess, electrically connecting a second pad of the interposer substrate and the first pad of the main substrate, and filling a gap between the interposer substrate and the main substrate with an underfill. The recess exposes a first pad of the main substrate. A second pad of interposer substrate and the first pad of the main substrate are made of the same metal and formed in different outer surface profiles. The underfill entirely touches side surfaces and a bottom surface of the interposer substrate.

公开(公告)号：US11430768B2

公开(公告)日：2022-08-30

申请号：US17182258

申请日：2021-02-23

Applicant: Unimicron Technology Corp.

Inventor： Tzu-Hsuan Wang ,  Chen-Hsien Liu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/433 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

Abstract: A chip package structure includes a wiring board, a first chip, a second chip, a thermally conductive material, a molding compound and a heat dissipation part. The wiring board includes a plurality of circuit pads. The first chip is mounted on the wiring board and is electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the wiring board. The thermally conductive material is located on the wiring board and penetrates the second chip and the first chip to extend to the wiring board. The molding compound is disposed on the wiring board, and the heat dissipation part is disposed on the molding material and thermally coupled to the thermally conductive material.