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    비피에스지막 형성방법
    61.
    发明公开
    비피에스지막 형성방법 无效
    形成BPSG层的方法

    公开(公告)号：KR1020020094718A

    公开(公告)日：2002-12-18

    申请号：KR1020010033104

    申请日：2001-06-13

    Applicant: 삼성전자주식회사

    Inventor： 한재현

    IPC: H01L21/31

    Abstract: PURPOSE: A method for forming a BPSG(Boro Phosphorous Silicate Glass) layer is provided to effectively reduce a stress of a semiconductor substrate. CONSTITUTION: After loading a semiconductor substrate in a processing chamber(200), a BPSG layer having a thickness of 8000Å is formed on the semiconductor substrate at the temperature of 350-450°C(202). After rising the temperature of the processing chamber to 650-750°C(204), a BPSG layer having a thickness of 8000Å is formed on the semiconductor substrate after falling the temperature in the processing chamber to 350-450°C(206). After rising the temperature of the processing chamber to 650-750°C (208), a BPSG layer having a thickness of 4000Å is formed on the semiconductor substrate after falling the temperature in the processing chamber to 350-450°C(210).

    Abstract translation: 目的：提供一种形成BPSG（Boro Phosphorous Silicate Glass）层的方法，以有效降低半导体衬底的应力。 构成：在处理室（200）中加载半导体衬底之后，在350-450℃（202）的温度下，在半导体衬底上形成厚度为8000的BPSG层。 在将处理室的温度升高到650-750℃（204）之后，在处理室中的温度降至350-450℃（206）之后，在半导体衬底上形成厚度为8000的BPSG层。 在将处理室的温度升高到650-750℃（208）之后，在处理室中的温度降至350-450℃（210）之后，在半导体衬底上形成厚度为4000埃的BPSG层。

    반도체 장치의 미세 패턴들간의 갭을 채우는 절연층형성방법
    62.
    发明公开
    반도체 장치의 미세 패턴들간의 갭을 채우는 절연층형성방법 无效
    在半导体器件的精细图案之间制作绝缘层填充缝隙的方法

    公开(公告)号：KR1020020044001A

    公开(公告)日：2002-06-14

    申请号：KR1020000073485

    申请日：2000-12-05

    Applicant: 삼성전자주식회사

    Inventor： 한재현 ,  안태혁 ,  강호규

    IPC: H01L21/31

    Abstract: PURPOSE: A method for fabricating an insulation layer filling a gap between fine patterns of a semiconductor device is provided to prevent an insulation defect like a bridge in a subsequent process, by preventing a void inside the gap between fine material layer patterns. CONSTITUTION: Plasma excited from reaction gas including silicon source gas and etchant source gas is supplied to a semiconductor substrate(100) having the material layer pattern(200). Bias is applied to the rear surface of the semiconductor substrate continuously or as a pulse state to induce deposition and etch processes caused by plasma.

    Abstract translation: 目的：提供填充半导体器件的精细图案之间的间隙的绝缘层的方法，以防止在后续工艺中的桥接的绝缘缺陷，通过防止精细材料层图案之间的间隙内的空隙。 构成：从包括硅源气体和蚀刻剂源气体的反应气体激发的等离子体被供给到具有材料层图案（200）的半导体衬底（100）。 偏置被连续施加到半导体衬底的后表面，或作为脉冲状态，以引起由等离子体引起的沉积和蚀刻过程。

    저유전 층간절연막을 이용한 콘택홀 형성방법
    63.
    发明公开
    저유전 층간절연막을 이용한 콘택홀 형성방법 无效
    使用具有低介电常数的中间层介质形成接触孔的方法

    公开(公告)号：KR1020010094000A

    公开(公告)日：2001-10-31

    申请号：KR1020000017352

    申请日：2000-04-03

    Applicant: 삼성전자주식회사

    Inventor： 한재현

    IPC: H01L21/28

    Abstract: PURPOSE: A method of forming a contact hole is provided to improve a contact resistance by increasing the bottom area of the contact hole using an MSSQ(MethylSilSesQuioxane) having low dielectric constant as an interlayer dielectric. CONSTITUTION: A first interlayer dielectric(102b) made of an MSSQ including Si-O-C and a second interlayer dielectric(104) are sequentially formed on a semiconductor substrate(100). The first and second interlayer dielectrics(102b,104) are selectively etched by using a photoresist pattern as a mask so as to form a contact hole having an aspect ratio of 2.5 more than. The resultant structure is then performed by ashing using plasma including oxygen, thereby removing the photoresist pattern. At this time, the both sides of the first interlayer dielectric(102b) made of the MSSQ are formed a damaged layer. The damage layer is then etched by using HF etchant, so that a contact hole having increased area is formed.

    Abstract translation: 目的：提供形成接触孔的方法，通过使用具有低介电常数的MSSQ（MethylSilSesQuioxane）作为层间电介质，增加接触孔的底部面积来提高接触电阻。 构成：在半导体衬底（100）上依次形成由包括Si-O-C的MSSQ和第二层间电介质（104）制成的第一层间电介质（102b）。 通过使用光致抗蚀剂图案作为掩模来选择性地蚀刻第一和第二层间电介质（102b，104），以便形成纵横比为2.5以上的接触孔。 然后通过使用包含氧的等离子体的灰化进行所得结构，从而去除光致抗蚀剂图案。 此时，由MSSQ构成的第一层间电介质（102b）的两侧形成损伤层。 然后通过使用HF蚀刻剂来蚀刻损伤层，从而形成具有增加的面积的接触孔。

    반도체 장치의 제조공정에서 패드층 형성방법
    64.
    发明公开
    반도체 장치의 제조공정에서 패드층 형성방법 无效
    在半导体器件制造工艺中形成焊盘层的方法

    公开(公告)号：KR1019980068043A

    公开(公告)日：1998-10-15

    申请号：KR1019970004475

    申请日：1997-02-14

    Applicant: 삼성전자주식회사

    Inventor： 한재현

    IPC: H01L21/302

    Abstract: 본 발명은 반도체장치의 제조공정에서 패드층 형성방법에 관해 개시한다.
    본 발명에 의한 반도체장치의 제조공정에서 패드층 형성방법에서는 듀얼 패드층을 형성하더라고 패드층 영역을 한정하는 감광막 패턴의 측면에 상기 제2 스페이서를 형성하고 이를 식각마스크로 하여 감광막 패턴아래에 형성된 물질막들을 패터닝함으로써 형성되는 두 패드층의 폭을 상기 제2 스페이서 폭의 두배정도 넓게 형성할 수 있다. 또한, 상기 감광막 패턴아래의 물질막을 패터닝하는 과정에서 상기 게이트 전극의 상부에는 제1 절연막이 덮혀 있으므로 충분한 과도식각을 실시하여 상기 두 패드층간에 브리지가 형성되는 것을 방지할 수 있다.
    이 결과 폭이 넓고 상호 브리지가 형성되지 않은 듀얼 패드층이 형성된다. 이러한 결과는 후속 상기 두 패드층의 계면을 노출시키는 공정에서 공정마진을 넓게 가져갈 수 있으므로 고 집적화속에서도 반도체장치의 제조공정을 쉽게 가져갈 수 있다.

    플라즈마 이온 주입시스템
    70.
    发明授权
    플라즈마 이온 주입시스템 失效
    基于等离子体离子植入系统

    公开(公告)号：KR100855002B1

    公开(公告)日：2008-08-28

    申请号：KR1020070050132

    申请日：2007-05-23

    Applicant: 삼성전자주식회사

    Inventor： 이영동 ,  유리톨마체프 ,  블라디미르볼리네츠 ,  바실리파쉬코프스키 ,  안드레이우샤코프 ,  금경수 ,  한재현 ,  김동철 ,  조형철

    IPC: H01L21/265

    CPC classification number: H01J37/32449 ,  H01J37/32357 ,  H01J37/32412 ,  H01J37/3244 ,  H01J37/3255 ,  H01J37/32862 ,  H01L21/2236

    Abstract: A system for implanting plasma ions is provided to generate only the ions and polymer radicals necessary for an ion implantation process and easily control implanted plasma ions by generating plasma having an characteristic advantageous for an ion implantation process as compared with an ICP(inductively coupled plasma) process. A process target(501) is positioned in a vacuum chamber(500) having a reaction space in which plasma is generated. A first gas supply apparatus supplies reaction gas to the vacuum chamber. A second gas supply apparatus supplies cleaning gas to the vacuum chamber. Upper and lower electrodes(502,553) are installed in the vacuum chamber, confronting each other. A conductive ring(551) is installed in the periphery of the process target. An RF supply apparatus supplies RF power to the upper electrode to generate plasma. A high voltage supply apparatus supplies a high voltage to the process target, the lower electrode and the conductive ring. The first and second gas supply apparatuses can be installed in the sidewall(504) of the vacuum chamber, confronting each other.

    Abstract translation: 提供了用于植入等离子体离子的系统，以仅产生离子注入工艺所需的离子和聚合物自由基，并且通过产生具有有利于离子注入工艺的特性的等离子体容易地控制注入的等离子体离子，与ICP（电感耦合等离子体）相比， 处理。 处理目标（501）位于具有产生等离子体的反应空间的真空室（500）中。 第一气体供给装置向真空室供给反应气体。 第二气体供给装置向真空室供给清洁气体。 上下电极（502,553）安装在真空室中，彼此面对。 导电环（551）安装在处理靶的周围。 RF供给装置向上部电极提供RF功率以产生等离子体。 高压电源装置向工艺靶，下电极和导电环提供高电压。 第一和第二气体供给装置可以安装在真空室的侧壁（504）中，彼此面对。

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