公开(公告)号：KR101394553B1

公开(公告)日：2014-05-14

申请号：KR1020070113790

申请日：2007-11-08

Applicant: 삼성전자주식회사

Inventor： 유태광 ,  한정욱 ,  김용태

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11524

Abstract: 비휘발성 메모리 소자 및 그 형성방법이 제공된다. 상기 비휘발성 메모리 소자는 반도체 기판, 상기 반도체 기판에 활성 영역을 정의하며 상기 활성 영역의 상부 측면을 노출하도록 상기 반도체 기판의 상부면보다 낮은 상부면을 가지는 소자분리막, 상기 활성 영역 및 상기 소자분리막을 가로지르는 센스 라인, 및 상기 센스 라인과 이격되며, 상기 활성 영역 및 상기 소자분리막을 가로지르는 워드 라인을 포함한다.
EEPROM, 셀 전류, 워드 라인

公开(公告)号：KR1020100081633A

公开(公告)日：2010-07-15

申请号：KR1020090000944

申请日：2009-01-06

Applicant: 삼성전자주식회사

Inventor： 유태광 ,  한정욱 ,  김용태

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881 ,  H01L21/67075

Abstract: PURPOSE: A non-volatile memory device and a method for manufacturing the same are provided to increase the performance of the device by forming a floating gate electrode, in which electrons are stored, on the upper side and the lateral side of a channel in order to three dimensionally surrounds an active region. CONSTITUTION: An active region is formed on a substrate(10). An element isolation layer defines the active region. The element isolation layer is formed on both sides of a channel which is located on the substrate. The height of the element isolation layer is lower than that of the upper surface of the active region. A first dielectric layer(14), a second dielectric layer(20), and a control gate electrode are successively formed on the upper side of the active region. A floating gate electrode(18) is formed on both sides of the active region.

Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，以通过在通道的上侧和外侧依次形成存储有电子的浮栅电极来提高器件的性能 三维地围绕有源区域。 构成：在衬底（10）上形成有源区。 元件隔离层定义有源区域。 元件隔离层形成在位于基板上的通道的两侧。 元件隔离层的高度低于有源区的上表面的高度。 第一电介质层（14），第二电介质层（20）和控制栅电极依次形成在有源区的上侧。 在有源区的两侧形成有浮栅电极（18）。

公开(公告)号：KR100886429B1

公开(公告)日：2009-03-02

申请号：KR1020070046615

申请日：2007-05-14

Applicant: 삼성전자주식회사

Inventor： 양승진 ,  한정욱 ,  김용태 ,  최용석 ,  권혁기

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L27/105 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 본 발명은 반도체 소자 및 제조방법에 관한 것으로, 제1 회로를 포함하는 제1 반도체층과, 상기 제1 반도체층 위에 적층되고 제2 회로를 포함하는 제2 반도체층과, 상기 제1 및 제2 반도체층의 일부를 관통하고 상기 제1 및 제2 회로를 전기적으로 연결시키는 비아를 포함하는 것을 특징으로 한다. 본 발명에 의하면, 서로 다른 기판에 게이트 절연막의 두께가 상이한 로직 회로와 메모리 회로를 각각 형성하고, 이들 기판을 적층시키고, 관통 비아를 통해 로직 회로와 메모리 회로를 전기적으로 연결시킨다.
반도체 소자, 관통 비아, 로직 회로, 메모리 회로

Abstract translation: 本发明涉及一种半导体器件及其制造方法，包括：第一半导体层，包括第一电路;第二半导体层，堆叠在第一半导体层上并且包括第二电路; 以及贯穿半导体层的一部分并电连接第一和第二电路的通孔。 根据本发明，在不同的衬底上分别形成具有不同厚度的栅极绝缘膜的逻辑电路和存储电路，这些衬底被层叠，并且逻辑电路和存储电路通过通孔电连接。

公开(公告)号：KR1020090004155A

公开(公告)日：2009-01-12

申请号：KR1020070068145

申请日：2007-07-06

Applicant: 삼성전자주식회사

Inventor： 양승진 ,  한정욱 ,  최용석 ,  권혁기 ,  권배성

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/7885 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L21/28141 ,  H01L27/10891

Abstract: The non-volatile memory device and a method of forming the same are the protrusion having the edge forming the semiconductor substrate which is perpendicular to the side of the floating gate. The gate insulating layer(112) is formed on the semiconductor substrate(100). The floating gate(130) is formed on the gate insulating layer. The word line(140) is arranged in one side of the floating gate. The protrusion is formed in the first side surface of the floating gate facing the word line. The projection part is positioned to the word line. The end of protrusion comprises the edge which is perpendicular to the upper side of the semiconductor substrate.

Abstract translation: 非易失性存储器件及其形成方法是具有形成半导体衬底的边缘的突起，其垂直于浮动栅极的侧面。 栅极绝缘层（112）形成在半导体衬底（100）上。 浮置栅极（130）形成在栅极绝缘层上。 字线（140）布置在浮动栅极的一侧。 突起形成在面对字线的浮动栅极的第一侧表面中。 投影部分位于字线上。 突起的端部包括垂直于半导体衬底的上侧的边缘。

公开(公告)号：KR1020080079010A

公开(公告)日：2008-08-29

申请号：KR1020070019000

申请日：2007-02-26

Applicant: 삼성전자주식회사

Inventor： 양승진 ,  한정욱 ,  최용석 ,  권혁기

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  G11C16/10 ,  H01L21/265 ,  H01L21/28273

Abstract: A multi-bit flash memory cell, and a method for driving and manufacturing the same are provided to erase or program four different threshold voltages by applying a suitable bias to a source region, first and second drain regions, and a control gate electrode. A multi-bit flash memory cell includes first and second drain regions(D1,D2), a source region(S), conductive floating gates(9a,9b,9c), and a control gate electrode(13a). The first and second drain regions are formed on a semiconductor substrate(1). The source region is formed on the semiconductor substrate between the first and second drain regions, and is spaced apart from the first and second drain regions by first and second distances, respectively. The conductive floating gates cover the semiconductor substrate between the first and second drain regions. The control gate electrode is stacked on the conductive floating gate. The first distance is different from the second distance or a first junction depth is different from a second junction depth. The control gate electrode has a control gate extension portion disposed on the source region.

Abstract translation: 提供多位闪存单元及其驱动和制造方法，以通过向源区域，第一和第二漏极区域以及控制栅极电极施加合适的偏置来擦除或编程四个不同的阈值电压。 多位闪存单元包括第一和第二漏极区域（D1，D2），源极区域（S），导电浮动栅极（9a，9b，9c）和控制栅电极（13a）。 第一和第二漏极区域形成在半导体衬底（1）上。 源极区域形成在第一和第二漏极区域之间的半导体衬底上，并且分别与第一和第二漏极区域分开第一和第二距离。 导电浮置栅极覆盖第一和第二漏极区域之间的半导体衬底。 控制栅电极堆叠在导电浮栅上。 第一距离与第二距离不同或第一结深不同于第二结深度。 控制栅极具有设置在源极区上的控制栅延伸部。

公开(公告)号：KR1020080031092A

公开(公告)日：2008-04-08

申请号：KR1020060097469

申请日：2006-10-03

Applicant: 삼성전자주식회사

Inventor： 전희석 ,  한정욱

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/11253 ,  G11C11/005 ,  G11C16/0433 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

Abstract: A mask ROM, a mask ROM embedded EEPROM and a manufacturing method thereof are provided to code a mask ROM cell into an on-cell and an off-cell by transforming a mask for forming a cell diffusion area through an ion implanting process. A peripheral circuit area(A), an EEPROM area(B) and a mask ROM area(C) are defined on a semiconductor substrate(50). And an active area is defined on the semiconductor substrate. An insulating layer(52) is formed on the active area. A transistor of the peripheral circuit is formed at the peripheral circuit area, an EEPROM cell is formed at the EEPROM area, and mask ROM on/off-cells are formed at the mask ROM area. A gate pattern(Gp,60) is formed on the peripheral circuit area, and drain/source areas(64s,64d) of the peripheral circuit are formed on the substrate at both sides of the gate pattern. The EEPROM cell has a structure in which a selection transistor and a memory transistor are connected in serial. The gate pattern of the selection transistor(Gs) and the gate pattern of the memory transistor(Gm) are located with a predetermined distance in the EEPROM. The mask ROM cell has a similar structure to the EEPROM cell. The on-cell of the mask ROM has the same structure of the EEPROM cell, and the off-cell is able to be the same structure excluding the cell active area.

Abstract translation: 提供掩模ROM，掩模ROM嵌入式EEPROM及其制造方法，通过离子注入工艺转换形成单元扩散区域的掩模，将掩模ROM单元编码为单元格内和外单元。 外围电路区域（A），EEPROM区域（B）和掩模ROM区域（C）被限定在半导体衬底（50）上。 并且在半导体衬底上限定有源区。 在有源区上形成绝缘层（52）。 外围电路的晶体管形成在外围电路区域，EEPROM单元形成在EEPROM区域，掩模ROM开/关单元形成在掩模ROM区域。 在外围电路区域上形成栅极图案（Gp，60），并且在栅极图案的两侧在基板上形成外围电路的漏极/源极区域（64s，64d）。 EEPROM单元具有串联连接选择晶体管和存储晶体管的结构。 选择晶体管（Gs）的栅极图案和存储晶体管（Gm）的栅极图案以规定的距离位于EEPROM中。 掩模ROM单元具有与EEPROM单元相似的结构。 掩模ROM的电容单元具有与EEPROM单元相同的结构，并且离电池能够是除了电池活性区域以外的相同结构。

公开(公告)号：KR1020080025560A

公开(公告)日：2008-03-21

申请号：KR1020060090190

申请日：2006-09-18

Applicant: 삼성전자주식회사

Inventor： 김광태 ,  한정욱 ,  유태광 ,  박지훈 ,  홍은미

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/2436

Abstract: A nonvolatile memory device and a method for fabricating the same are provided to prevent mis-alignment due to photolithography by implementing a spacer typed floating gate at a protruded source region. A nonvolatile memory device includes a source region(160) and a memory transistor. The source region is formed by extruding at an active region of a semiconductor substrate. The memory transistor includes a floating gate(110b), a dielectric(112b), and a control gate(114b). The floating gate is formed by arranging at a side wall of the source region. The dielectric is formed on the floating gate by overlapping with a part of the source region. The control gate is formed on the dielectric.

Abstract translation: 提供一种非易失性存储器件及其制造方法，以通过在突出的源极区域上实施间隔型浮动栅极来防止由于光刻而引起的错误对准。 非易失性存储器件包括源区（160）和存储晶体管。 源极区域通过在半导体衬底的有源区域处挤出而形成。 存储晶体管包括浮置栅极（110b），电介质（112b）和控制栅极（114b）。 浮动栅极通过在源极区域的侧壁处布置而形成。 通过与源区域的一部分重叠而在浮栅上形成电介质。 控制栅极形成在电介质上。

公开(公告)号：KR1020080021885A

公开(公告)日：2008-03-10

申请号：KR1020060085025

申请日：2006-09-05

Applicant: 삼성전자주식회사

Inventor： 박원호 ,  한정욱 ,  김용태

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L21/28273

Abstract: An electrically erasable and programmable read only memory device and fabricating method thereof are provided to alternatively serve as a memory transistor and a selection transistor in response to an applied signal using first and second transistors having the same structure. A pair of transistors including first and second transistors(190,193) are formed on a substrate(100). The first and second transistors have substantially the same structure, and are configured to alternately serve as a memory transistor and a selection transistor according to an applied signal. The first transistor has a tunnel insulating layer(103) formed on the substrate. A first gate structure formed on the tunnel insulating layer, a first drain region(181) formed at a first portion of the substrate adjacent to the first gate structure, and a common source region(178) formed on a portion of the substrate located between the first transistor and the second transistor. The second transistor has a second gate structure formed on the tunnel insulating layer, and a second drain region formed on a second portion of the substrate adjacent to the second gate structure.

Abstract translation: 提供电可擦除和可编程的只读存储器件及其制造方法，作为响应于使用具有相同结构的第一和第二晶体管的施加信号而用作存储晶体管和选择晶体管。 包括第一和第二晶体管（190,193）的一对晶体管形成在衬底（100）上。 第一和第二晶体管具有基本上相同的结构，并且被配置成根据施加的信号交替地用作存储晶体管和选择晶体管。 第一晶体管具有形成在基板上的隧道绝缘层（103）。 形成在所述隧道绝缘层上的第一栅极结构，形成在与所述第一栅极结构相邻的所述衬底的第一部分处的第一漏极区域（181）和形成在所述衬底的位于所述第一栅极结构 第一晶体管和第二晶体管。 第二晶体管具有形成在隧道绝缘层上的第二栅极结构，以及形成在与第二栅极结构相邻的衬底的第二部分上的第二漏极区。

公开(公告)号：KR1020080001284A

公开(公告)日：2008-01-03

申请号：KR1020060059608

申请日：2006-06-29

Applicant: 삼성전자주식회사

Inventor： 양승진 ,  한정욱 ,  최용석 ,  권혁기

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/0692 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L21/28282

Abstract: A nonvolatile memory IC(Integration Circuit) having a vertical channel and a method for manufacturing the same are provided to increase the integration degree by forming two nonvolatile memory cells to a single semiconductor pillar. A plurality of semiconductor pillars(120a-120e) are arranged on a substrate by matrix type. A first and a second charge storage structures(120,140) are oppositely formed at outside surface of each semiconductor pillar. The first and the second charge storage structures further include a tunneling pattern, a charge storage pattern, and a shielding pattern. A first conductive line(150) is elongated to a first direction in order to form on the first charge storage structure, and a second conductive line(160) is elongated to the first direction to form on the second charge storage structure. A first junction region(112) is formed in the substrate between the semiconductor pillars adjacent to a second direction. A second junction region is formed on the each semiconductor pillar.

Abstract translation: 提供具有垂直通道的非易失性存储器IC（集成电路）及其制造方法，以通过将单个半导体柱形成两个非易失性存储单元来提高积分度。 多个半导体柱（120a〜120e）通过矩阵型配置在基板上。 第一和第二电荷存储结构（120,140）在每个半导体柱的外表面处相对地形成。 第一和第二电荷存储结构还包括隧穿图案，电荷存储图案和屏蔽图案。 为了在第一电荷存储结构上形成第一导电线（150），以在第一方向上延伸，并且第二导线（160）在第一方向上被拉长以在第二电荷存储结构上形成。 在与第二方向相邻的半导体柱之间的衬底中形成第一接合区域（112）。 在每个半导体柱上形成第二结区。

公开(公告)号：KR100757326B1

公开(公告)日：2007-09-11

申请号：KR1020060099600

申请日：2006-10-13

Applicant: 삼성전자주식회사

Inventor： 유현기 ,  한정욱 ,  전희석 ,  최성곤 ,  서보영 ,  전창민 ,  류지도

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/823493

Abstract: A non-volatile memory device and a method for fabricating and operating the same are provided to prevent bad operation due to decrease of on current by forming a depletion channel region in a memory transistor. A sensing line(132) and a word line(130) are formed on a substrate(100), and has a tunnel oxide layer(114), a first conductive layer pattern(116a), a dielectric layer pattern(118a) and a second conductive layer pattern(120a). A depletion channel region(112) is formed under a surface of the substrate which is opposite to a bottom surface of the sensing line. An impurity region(140) is formed under the surface of the substrate which is partially by the sensing line and the word line.

Abstract translation: 提供一种非易失性存储器件及其制造和操作方法，以通过在存储晶体管中形成耗尽沟道区域来防止由于导通电流的降低导致的不良操作。 感测线（132）和字线（130）形成在基板（100）上，并且具有隧道氧化物层（114），第一导电层图案（116a），电介质层图案（118a）和 第二导电层图案（120a）。 在衬底的与感测线的底表面相对的表面下方形成耗尽沟道区（112）。 在衬底的表面下部分地由感测线和字线形成杂质区（140）。