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Patent Agency Ranking
公开(公告)号：KR101236483B1
公开(公告)日：2013-02-22
申请号：KR1020110096283
申请日：2011-09-23
Applicant: 전자부품연구원
CPC classification number: H01L2224/10
Abstract: PURPOSE: A laminated semiconductor package and a manufacturing method thereof are provided to reduce the thickness of a package by arranging a bare chip at the same height as a ball bump or a pillar bump. CONSTITUTION: The upper side of a first interposer is combined with a first semiconductor chip(110) by first solder balls(120). The lower side of the first interposer is combined with a second semiconductor chip(150). A second semiconductor chip is formed between second solder balls(140). The upper side of a second interposer has a space for receiving the second semiconductor chip. The lower side of the second interposer is combined with a third semiconductor chip located between third solder balls.
Abstract translation: 目的：提供一种层叠半导体封装及其制造方法，通过将裸芯片设置在与球凸块或柱凸起相同的高度上来减小封装的厚度。 构成：通过第一焊球（120）将第一插入件的上侧与第一半导体芯片（110）组合。 第一插入器的下侧与第二半导体芯片（150）组合。 在第二焊球（140）之间形成第二半导体芯片。 第二插入器的上侧具有用于接收第二半导体芯片的空间。 第二插入器的下侧与位于第三焊球之间的第三半导体芯片组合。
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公开(公告)号：KR101225663B1
公开(公告)日：2013-01-23
申请号：KR1020110045238
申请日：2011-05-13
Applicant: 전자부품연구원
CPC classification number: H01L21/568 , H01L2224/04105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2924/15153 , H01L2924/181 , H01L2924/00 , H01L2224/18 , H01L2924/00012
Abstract: 본 발명은 칩 내장형 기판 제조 방법이 개시된다. 일 실시 예에서, 금속 박막 상부에 반도체 칩 안착용 감광성 드라이 필름을 라미네이트하는 (a) 단계; 상기 금속 박막 하부에 얼라인먼트 패턴용 감광성 드라이 필름을 라미네이트하는 (b) 단계; 상기 반도체 칩 안착용 감광성 드라이 필름에 반도체 칩을 삽입하기 위한 반도체 칩 삽입구를 형성하는 (c) 단계; 상기 얼라인먼트 패턴용 감광성 드라이 필름에 얼라인먼트 패턴을 형성하는 (d) 단계; 상기 얼라인먼트 패턴이 형성된 부분만을 남기고 금속 박막을 에칭하여 얼라인먼트 포스트를 형성하는 (e) 단계; 상기 반도체 칩 삽입구가 형성된 감광성 드라이 필름 상에 반도체 칩 이탈 방지용 감광성 드라이 필름을 라미네이트하고, 남아있는 얼라인먼트 패턴용 감광성 드라이 필름을 제거하는 (f) 단계; 반도체 칩이 상기 반도체 칩 삽입구에 삽입된 후에, 상기 반도체 칩 안착용 감광성 드라이 필름 상에 패키징재를 적층하는 (g)단계; 남아 있는 감광성 드라이 필름을 제거하는 (h)단계; 및 상기 반도체 칩 하부를 패키징재로 적층하는 (i)단계를 포함하는 것으로, 반도체 칩을 지지하기 위한 코어를 구비하지 않고서도 반도체 칩을 패키징할 수 있는 것입니다.
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公开(公告)号：KR1020120127033A
公开(公告)日：2012-11-21
申请号：KR1020110045238
申请日：2011-05-13
Applicant: 전자부품연구원
CPC classification number: H01L21/568 , H01L2224/04105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2924/15153 , H01L2924/181 , H01L2924/00 , H01L2224/18 , H01L2924/00012
Abstract: PURPOSE: A manufacturing method for a chip embedded substrate is provided to easily arrange a semiconductor chip in an semiconductor chip inlet hole by precisely making the semiconductor chip inlet hole using a dry film. CONSTITUTION: A photosensitive dry film(200) for mounting a semiconductor chip is laminated on an upper portion of a metal thin film(100). The photosensitive dry film for an alignment pattern is laminated on a lower portion of the metal thin film. A semiconductor chip inlet hole is formed for inserting the semiconductor chip into the photosensitive dry film for mounting the semiconductor chip. An alignment pattern is formed on the photosensitive dry film for the alignment pattern. An alignment post is formed by etching the metal thin film except for a portion where the alignment pattern is formed.
Abstract translation: 目的：提供一种用于芯片嵌入式基板的制造方法，通过使用干膜精确地制造半导体芯片入口孔，将半导体芯片容易地布置在半导体芯片入口孔中。 构成：用于安装半导体芯片的感光干膜（200）层压在金属薄膜（100）的上部。 用于对准图案的感光性干膜层叠在金属薄膜的下部。 形成用于将半导体芯片插入到用于安装半导体芯片的感光干膜中的半导体芯片入口孔。 在对准图案的感光性干膜上形成取向图案。 通过蚀刻除了形成对准图案的部分之外的金属薄膜形成定位柱。
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公开(公告)号：KR1020120078686A
公开(公告)日：2012-07-10
申请号：KR1020120056923
申请日：2012-05-29
Applicant: 전자부품연구원
CPC classification number: H01L2224/24 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: A semiconductor package and a manufacturing method thereof are provided to perform a through via with low loss, a high frequency passive device with high performance and a transmission line on a silicon substrate. CONSTITUTION: A first hole is formed on a silicon substrate(S110). A first metal layer is formed on the silicon substrate formed the first hole(S115). An insulating layer is formed on the first metal layer(S120). A second hole which size is smaller than the first hole size is formed at the first hole position(S130). A second metal layer is formed on the insulating layer by filing the second hole(S140). The first metal layer and the second metal layer are exposed to the lower surface of the silicon substrate(S150).
Abstract translation: 目的：提供一种半导体封装及其制造方法，以低损耗执行通孔，具有高性能的高频无源器件和硅衬底上的传输线。 构成：在硅衬底上形成第一孔（S110）。 在形成第一孔的硅衬底上形成第一金属层（S115）。 在第一金属层上形成绝缘层（S120）。 在第一孔位置处形成尺寸小于第一孔尺寸的第二孔（S130）。 通过填充第二孔而在绝缘层上形成第二金属层（S140）。 第一金属层和第二金属层暴露于硅基板的下表面（S150）。
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公开(公告)号：KR1020120072451A
公开(公告)日：2012-07-04
申请号：KR1020100134210
申请日：2010-12-24
Applicant: 전자부품연구원
CPC classification number: H01L2224/04105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/14 , H01L2924/00 , H01L2224/18 , H01L2924/00012
Abstract: PURPOSE: A multilayer semiconductor device and a manufacturing method thereof are provided to prevent voids by connecting signal lines between unit semiconductor packages using a metal pin insertion method. CONSTITUTION: A top unit semiconductor package(200) is formed on a bottom unit semiconductor package(100). An organic layer(230) is formed on the lower side of the top unit semiconductor package. A metal pin(130) of the bottom unit semiconductor package is inserted into a hole of the top unit semiconductor package. An insulation layer(240) is formed between the metal pin and a silicon substrate(210). A top unit semiconductor package(300) is stacked on the top unit semiconductor package.
Abstract translation: 目的：提供一种多层半导体器件及其制造方法，以通过使用金属针插入方法连接单元半导体封装之间的信号线来防止空隙。 构成：顶部单元半导体封装（200）形成在底部单元半导体封装（100）上。 在顶部单元半导体封装的下侧形成有机层（230）。 底部单元半导体封装的金属引脚（130）插入到顶部单元半导体封装的孔中。 在金属销和硅衬底（210）之间形成绝缘层（240）。 顶部单元半导体封装（300）堆叠在顶部单元半导体封装上。
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