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公开(公告)号：KR1020100031831A
公开(公告)日：2010-03-25
申请号：KR1020080090653
申请日：2008-09-16
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A multi-stage successive approximation register analog to digital converter and an analog to digital conversion method thereof are provided to reduce analog to digital conversion time by improving an analog to digital conversion method. CONSTITUTION: A first SAR(Successive Approximation Register) ADC(300) changes a first analog input voltage to a n-bit digital. A second SAR ADC(310) changes the residual voltage of the first SAR ADC to a m-bit digital. The first SAR ADC changes the second analog input voltage to a digital during the residual voltage digital conversion period of the second SAR ADC.
Abstract translation: 目的：提供多级逐次逼近寄存器模数转换器及其模/数转换方法，以通过改进模数转换方法来减少模数转换时间。 构成：第一个SAR（逐次逼近寄存器）ADC（300）将第一个模拟输入电压更改为n位数字。 第二个SAR ADC（310）将第一个SAR ADC的残余电压改变为m位数字。 在第二个SAR ADC的剩余电压数字转换周期期间，第一个SAR ADC将第二个模拟输入电压改变为数字。
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公开(公告)号：KR1020100026839A
公开(公告)日：2010-03-10
申请号：KR1020080085999
申请日：2008-09-01
Applicant: 한국전자통신연구원
IPC: G05F3/24
CPC classification number: G05F3/30
Abstract: PURPOSE: A band gap reference voltage generator is provided to supply a reference voltage under 1V regardless of temperature variation while reducing the number of resistor which requires large area. CONSTITUTION: A band gap reference voltage generator includes a third and fourth resistance(R3-R4), a first and second bipolar transistor, and fourth and fifth NMOS transistor(M4-M5). The PMOS transistor has a gate and a source which are connected to a first node and a power terminal in common and has a drain connected to 2-4 nodes respectively. A feedback amplifier has inverting and non-inverting terminal which are connected to the second and third node respectively. The first and second bipolar transistor has emitters which are connected to a fifth node and the third node and has collector and base which are connected to the ground.
Abstract translation: 目的：提供带隙参考电压发生器，以提供低于1V的参考电压，而不管温度变化如何，同时减少需要大面积的电阻器的数量。 构成：带隙基准电压发生器包括第三和第四电阻（R3-R4），第一和第二双极晶体管以及第四和第五NMOS晶体管（M4-M5）。 PMOS晶体管具有栅极和源极，其共同连接到第一节点和电源端子，并且具有分别连接到2-4个节点的漏极。 反馈放大器具有分别连接到第二和第三节点的反相和非反相端子。 第一和第二双极晶体管具有连接到第五节点和第三节点并且具有连接到地的集电极和基极的发射极。
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Patent Agency Ranking
公开(公告)号：KR100916307B1
公开(公告)日：2009-09-10
申请号：KR1020070104108
申请日：2007-10-16
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1225 , H03M1/167
Abstract: 본 발명은 제1 디지털 신호를 아날로그 신호로 변환하는 DAC(Digital Analog Converter), 상기 DAC로부터 출력되는 신호 및 제1 SHA(Sample and Hold Amplifier)로부터 입력되는 아날로그 신호의 차를 구하는 감산기, 상기 감산된 신호를 증폭하는 증폭기, 상기 제1 SHA의 출력단 및 상기 증폭기의 입력단과 제1 스위치부를 통하여 결합하는 제1 커패시터부, 상기 증폭기의 입력단 및 상기 증폭기의 출력단과 제2 스위치부를 통하여 결합하는 제2 커패시터부 및 상기 증폭기의 입력단 및 상기 증폭기의 출력단과 제3 스위치부를 통하여 결합하는 제3 커패시터부를 포함하는 MDAC(Multiplying-DAC)가 구비된 것을 특징으로 하는 알고리즈믹 아날로그 디지털 변환기를 제공할 수 있다.
알고리즈믹 아날로그 디지털 변환기, MDAC-
公开(公告)号：KR1020090035358A
公开(公告)日：2009-04-09
申请号：KR1020070100603
申请日：2007-10-05
Applicant: 한국전자통신연구원
IPC: H03G3/20
CPC classification number: H03G1/0094 , H03F3/005 , H03F3/45475
Abstract: A switched capacitor variable gain amplifier is provided to reduce a voltage gain error due to capacitor mismatching by sharing a sampling capacitor in a sampling phase and an amplifying phase. A first sampling capacitor module(320A) and a second sampling capacitor module(320B) include a first sampling capacitor and a first variable capacitor and stores an input voltage in the sampling phase respectively. An operational amplifier amplifies the difference between input voltages in the amplifying phase. A first amplifying capacitor module(330A) and a second amplifying capacitor module(330B) share the first and second sampling capacitor modules and the first sampling capacitor and determine a voltage gain value of the input voltage according to the capacitance of a compensation capacitor, a second variable capacitor, and the shared first sampling capacitor. A plurality of sampling switches(340) and amplifying switches(350) are opened or closed in the sampling phase and the amplifying phase.
Abstract translation: 提供开关电容器可变增益放大器，以通过在采样阶段和放大阶段共享采样电容器来减少由于电容器失配引起的电压增益误差。 第一采样电容器模块（320A）和第二采样电容器模块（320B）包括第一采样电容器和第一可变电容器，并且分别在采样相位中存储输入电压。 运算放大器放大放大阶段的输入电压之差。 第一放大电容器模块（330A）和第二放大电容器模块（330B）共享第一和第二采样电容器模块和第一采样电容器，并根据补偿电容器的电容确定输入电压的电压增益值， 第二可变电容器和共享的第一采样电容器。 多个采样开关（340）和放大开关（350）在采样阶段和放大阶段被打开或关闭。
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公开(公告)号：KR1020090033980A
公开(公告)日：2009-04-07
申请号：KR1020070099082
申请日：2007-10-02
Applicant: 한국전자통신연구원
IPC: H03G3/20
CPC classification number: H03F3/45973 , H03F1/02 , H03F3/005 , H03F3/45475 , H03F2203/45136 , H03F2203/45514 , H04N5/335 , H04N5/378
Abstract: A dual CDS/PxGA(Correlated Double Sampling/Pixel Gain Amplifier) circuit is provided to obtain a wide variable gain by controlling the capacitance by the capacitor arrangement. A first sampling unit(310) samples a reset level and a data level of a first pixel. A second sampling unit(320) samples the reset level and the data level of a second pixel. An operational amplifier(330) receives a sampling value from the first sampling unit and the second sampling unit. The operational amplifier calculates the output signal of the first pixel and the output signal of the second pixel by using the sampling value and amplifies and outputs the calculated signal. The gain of the operational amplifier is decided based on the capacitance of the capacitors included in the first sampling unit and the second sampling unit.
Abstract translation: 提供双CDS / PxGA（相关双采样/像素增益放大器）电路以通过电容器布置控制电容来获得宽的可变增益。 第一采样单元（310）对第一像素的复位电平和数据电平进行采样。 第二采样单元（320）对第二像素的复位电平和数据电平进行采样。 运算放大器（330）从第一采样单元和第二采样单元接收采样值。 运算放大器通过使用采样值来计算第一像素的输出信号和第二像素的输出信号，并放大并输出计算出的信号。 运算放大器的增益基于包括在第一采样单元和第二采样单元中的电容器的电容来确定。
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公开(公告)号：KR1020090013312A
公开(公告)日：2009-02-05
申请号：KR1020070077314
申请日：2007-08-01
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M1/002 , H03M1/44
Abstract: A control method of pipeline analog/digital converter and a pipeline analog/digital converter are provided to minimize sampling mismatch by controlling a sampling point. A pipeline analog/digital converter does not use a shear sample-and-hold amplifier. A first stage of the pipeline analog/digital converter comprises an A/D converter and a residual signal generator. The A/D converter(420) samples the analog input signal and produces first sampling value. The A/D converter amplifies the first sampling value and converses the first sampling value to corresponding digital code. The residual signal generator(410) samples an analog input signal at the same time with the sampling by the A/D converter and produces second sampling value. While the A/D converter amplifies the first sampling value, the residual signal generator holds the second sampling value. The residual signal generator produces the residual signal by using the second sampling value and digital code and delivers the generated residual signal to the second stage.
Abstract translation: 提供管线模拟/数字转换器和流水线模拟/数字转换器的控制方法，以通过控制采样点来最小化采样失配。 管道模拟/数字转换器不使用剪切采样和保持放大器。 管线模拟/数字转换器的第一级包括A / D转换器和残余信号发生器。 A / D转换器（420）对模拟输入信号进行采样并产生第一采样值。 A / D转换器放大第一采样值并将第一采样值转换为相应的数字码。 残余信号发生器（410）通过A / D转换器的采样同时对模拟输入信号进行采样，并产生第二采样值。 当A / D转换器放大第一采样值时，剩余信号发生器保持第二采样值。 剩余信号发生器通过使用第二采样值和数字码产生残余信号，并将产生的残留信号传送到第二级。
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公开(公告)号：KR1020080024676A
公开(公告)日：2008-03-19
申请号：KR1020060089083
申请日：2006-09-14
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1225 , H03M1/168
Abstract: A multi-bit pipeline analog-to-digital converter is provided to decrease a chip size by arranging amplifiers between an SHA(Sampling and Holding Agent) and an MDAC of a first stage. A multi-bit pipeline analog-to-digital converter includes an SHA(10), an N-bit flash ADC(Analog Digital Converter)(20), an N-bit MDAC(30), and a 3-stage amplifier(AMP1). The SHA samples and holds an input analog voltage and removes a sampling error from an input voltage. The N-bit flash ADCs of first to K-th stages receive an analog signal and convert the analog signal to a digital signal. The N-bit MDACs of first to K-th stages convert a difference between an output digital signal from the N-bit flash ADC and the output signal from a previous stage into an analog signal and outputs the analog signal. The 3-stage amplifier is connected to the N-bit MDAC(Multiplying Digital to Analog Converter) output of the first stage at a first clock. At a second clock, the 3-stage amplifier is connected to an output of the SHA.
Abstract translation: 提供了一种多位流水线模数转换器，通过在SHA（采样和保持代理）与第一级的MDAC之间布置放大器来减小芯片尺寸。 多位流水线模数转换器包括SHA（10），N位闪存ADC（模拟数字转换器）（20），N位MDAC（30）和3级放大器（AMP1 ）。 SHA采样并保持输入模拟电压，并从输入电压中消除采样误差。 第一至第K级的N位闪存ADC接收模拟信号，并将模拟信号转换为数字信号。 第一至第K级的N位MDAC将来自N位闪存ADC的输出数字信号与来自前一级的输出信号之间的差转换为模拟信号，并输出模拟信号。 3级放大器在第一时钟连接到第一级的N位MDAC（乘法数模转换器）输出。 在第二个时钟，3级放大器连接到SHA的输出。
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