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公开(公告)号：CA2440101C
公开(公告)日：2006-03-21
申请号：CA2440101
申请日：2002-09-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER , ENGL BERNHARD
Abstract: Method for sampling phase control for the clock and data recovery of a data signal having the following steps, namely sampling (S1) of the received data signal with a first sampling signal comprising equidistant sampling pulses, minimization (S2, S3) of the phase deviation between the first sampling signal and the phase of the received data signal for the purpose of generating an adjusted second sampling signal, sampling (S4) of the received data signal with the second adjusted sampling signal for the purpose of generating sampling data values, integration (S5) of the sampling data values of the sampled data signal to form a summation value, and alteration (S9) of the phase of sampling pulses of the adjusted second sampling signal until the integrated summation value exceeds a threshold value (SW) that can be set.
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公开(公告)号：DE50203829D1
公开(公告)日：2005-09-08
申请号：DE50203829
申请日：2002-05-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： DUDA THOMAS , GAZSI LAJOS , GREGORIUS PETER , HINZ TORSTEN , RENNER MARTIN
Abstract: A method and a device for reconstructing data, clocked at a symbol rate, from a signal which has been distorted by transmission of a transmission link, are disclosed. The method or respectively, the device, being predominantly performed or implemented, respectively, by means of digital circuit technology in order to improve the quality of the data recovery. The method includes amplifying the signal amplitude attenuated by the transmission; filtering high-frequency interference frequencies above the symbol rate; discretizing the analog signal by means of an analog/digital converter; performing a cable approximation by means of a digitally implemented cable approximation filter in order to obtain an equalized signal; and recovering the data from the equalized signal by means of a phase-locked loop.
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公开(公告)号：DE102004014970A1
公开(公告)日：2004-12-16
申请号：DE102004014970
申请日：2004-03-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER
Abstract: The recovery unit has a feed forward phase tracking unit for tracking a sampling time to a center of a unit interval (UI) of a received serial data bit stream. A data recognition unit recovers the received data bit stream. The data recognition unit has parallel data recognition finite impulse response (FIR)-filters connected to a first-in-first-out (FIFO)-register. The FIFO register outputs the recovered data bit stream via an output terminal of the recovery unit. An independent claim is also included for a method for clock and data recovery of a received serial data bit stream.
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公开(公告)号：DE10215087B4
公开(公告)日：2004-08-19
申请号：DE10215087
申请日：2002-04-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER , PRETE EDOARDO , WALLNER PAUL
Abstract: A reference signal (6) is scanned within a period of a regulating signal at specific scan time points (S1-S5). By relying on all scan actions (A0-A4) for the reference signal taken within the regulating signal period, output signals (PD0-PD3) are generated so as to assume one of three conditions and are suppressed in the event of a fault. An Independent claim is also included for a device.
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公开(公告)号：DE10215087A1
公开(公告)日：2003-10-30
申请号：DE10215087
申请日：2002-04-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER , PRETE EDOARDO , WALLNER PAUL
Abstract: A reference signal (6) is scanned within a period of a regulating signal at specific scan time points (S1-S5). By relying on all scan actions (A0-A4) for the reference signal taken within the regulating signal period, output signals (PD0-PD3) are generated so as to assume one of three conditions and are suppressed in the event of a fault. An Independent claim is also included for a device.
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Patent Agency Ranking
公开(公告)号：CA2440101A1
公开(公告)日：2003-08-07
申请号：CA2440101
申请日：2002-09-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER , ENGL BERNHARD
Abstract: Disclosed is a method for controlling the sampling phase in order to recover the tact pulse and data of a data signal, comprising the following steps: - the received data signal is sampled (S1) by a first sampling signal which consists of equidistant sampling pulses; - the phase variation between the first sampling signal and the phase of the received data signal is minimized (S2, S3) in order to generate an adjusted second sampling signal; - the received data signal is sampled (S4) by the second adjusted sampling signal in order to generate sampling data values; - the sampled data values of the sampled data signal are integrated (S5) to a cumulative value; and - the pha se of sampling pulses of the adjusted second sampling signal is modified until the integrated cumulative value exceeds a variable threshold value (SW).
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公开(公告)号：DE10157437A1
公开(公告)日：2003-06-12
申请号：DE10157437
申请日：2001-11-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD , GREGORIUS PETER
Abstract: The arrangement has a commutator (1) for oversampling the received signal (S) so that several sample values of a bit cell transmitted with the signal are distributed successively to several output ports and output as intermediate signals, two stages (5,6) for combining first and second groups of intermediate signals to form data and clock recovery signals and a phase regulator (7,8) for setting sampling phases for oversampling the received signal.
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公开(公告)号：AU2002325905A1
公开(公告)日：2003-03-10
申请号：AU2002325905
申请日：2002-07-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GAZSI LAJOS , GREGORIUS PETER
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公开(公告)号：DE10164966B4
公开(公告)日：2010-04-29
申请号：DE10164966
申请日：2001-11-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD , GREGORIUS PETER
Abstract: The arrangement has a commutator (1) for oversampling the received signal (S) so that several sample values of a bit cell transmitted with the signal are distributed successively to several output ports and output as intermediate signals, two stages (5,6) for combining first and second groups of intermediate signals to form data and clock recovery signals and a phase regulator (7,8) for setting sampling phases for oversampling the received signal.
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公开(公告)号：DE102004032402B4
公开(公告)日：2007-12-27
申请号：DE102004032402
申请日：2004-07-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： JAKOBS ANDREAS , GREGORIUS PETER
IPC: G11C7/22
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