公开(公告)号：DE10105673C2

公开(公告)日：2003-04-17

申请号：DE10105673

申请日：2001-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8239

公开(公告)号：DE10152636A1

公开(公告)日：2003-01-30

申请号：DE10152636

申请日：2001-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: Semiconductor memory has capacitor devices (10-1,...., 10-4) each vertically extending from a substrate (20) and/or a passivating region (21) and/or a surface region (20a). A three dimensional arrangement or structure is formed for each capacitor device. An Independent claim is also included for a process for the production of a semiconductor memory. Preferred Features: The capacitor devices each have a first electrode arrangement (14), a second electrode arrangement (18) with a dielectric (16) arranged between the arrangements. The capacitor devices are a stacked structure of form part of a stacked structure.

公开(公告)号：DE10131626A1

公开(公告)日：2003-01-30

申请号：DE10131626

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239

Abstract: Production of a semiconductor memory comprises forming a semiconductor substrate (20), a passivating region (21) and/or a surface region (20a,21a) having a CMOS structure; forming capacitor arrangements (10-1, ..., 10-4) in the region of the substrate, passivating region and/or surface region; and providing first and second contact regions or plug regions (P1, P2) to contact with the capacitor arrangements. Preferred Features: The contact regions or plug regions are formed after forming the CMOS structure. Each capacitor arrangement has a first lower or bottom electrode device (14), a second upper or top electrode arrangement (18), and a dielectric (16) formed between the two electrode arrangements.

公开(公告)号：DE10131490A1

公开(公告)日：2003-01-16

申请号：DE10131490

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8239

Abstract: Production of capacitor arrangement comprises: removing lower layer (14) of a sequence of layers (14, 16) formed in surface region (20a) of semiconductor substrate (20) or passivating region (21) outside a region of predefined sites (K2) up to a reduced layer thickness (d); forming raised region (E) of lower layer; and forming subsequent layer (16) on lower layer, especially in the raised region. Preferred Features: The lower layer is removed by local deposition and/or local formation of a mask in the region of the predefined sites on the lower layer and by etching in the region of the mask. The layers of the layer sequence are applied in a common process step on the surface region of the substrate or on the passivating region, and then etched in a common process step and/or structured and/or after tempering.