中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.024 seconds)

    Semiconductor device and its manufacturing method
    1.
    发明专利
    Semiconductor device and its manufacturing method 有权
    半导体器件及其制造方法

    公开(公告)号：JP2005353829A

    公开(公告)日：2005-12-22

    申请号：JP2004172696

    申请日：2004-06-10

    Applicant: Infineon Technologies Ag ,  Toshiba Corp ,  インフィネオン テクノロジース アクチエンゲゼルシャフト ,  株式会社東芝

    Inventor： ITOKAWA HIROSHI ,  YAMAKAWA KOJI ,  BRUCHHAUS RAINER

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L31/062

    CPC classification number: H01L28/65 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that can suppress the occurrence of leakage currents in a capacitor using a dielectric film, and to provide a method of manufacturing the device.
    SOLUTION: The semiconductor device is provided with a semiconductor substrate (s) and a capacitor (10) having a lower electrode (200) provided above the substrate (s), the dielectric film (300) provided above the electrode (200), and an upper electrode (400) provided above the dielectric film (300). The upper electrode (400) is composed of an ABO
    3 perovskite-type oxide and contains a metal oxide containing the Ru element as a B-site element. In addition, the semiconductor device is also provided with a metallic film (120) containing the Ti element between the dielectric film (300) and upper electrode (400).
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 解决的问题：提供能够抑制使用电介质膜的电容器中的漏电流的发生的半导体器件，并提供制造该器件的方法。 解决方案：半导体器件设置有半导体衬底和具有设置在衬底上的下电极（200）的电容器（10），设置在电极（200）上方的电介质膜（300） ）和设置在电介质膜（300）上方的上电极（400）。 上电极（400）由ABO 3 SBO 3钙钛矿型氧化物构成，含有含Ru元素作为B位元素的金属氧化物。 此外，半导体器件还设置有在电介质膜（300）和上电极（400）之间含有Ti元素的金属膜（120）。 版权所有（C）2006，JPO＆NCIPI

    MEMORY ARCHITECTURE WITH SERIES GROUPED MEMORY CELLS
    3.
    发明申请
    MEMORY ARCHITECTURE WITH SERIES GROUPED MEMORY CELLS 审中-公开
    存储器架构与系列分组存储器单元

    公开(公告)号：WO2004059739A3

    公开(公告)日：2004-09-30

    申请号：PCT/EP0314637

    申请日：2003-12-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HILLIGER ANDREAS ,  BRUCHHAUS RAINER ,  WOHLFAHRT JOERG

    IPC: G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115

    CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/11507

    Abstract: An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.

    Abstract translation: 公开了具有串联结构的存储器阵列的IC。 串联组的存储器单元包括并联耦合到电容器的晶体管。 电容器包括第一和第二子电容器，一个堆叠在另一个的顶部。 在堆叠中提供具有两个或更多个子电容器的电容器有利地增加电容器的电容而不增加表面积。

    A METHOD OF ETCHING FERROELECTRIC DEVICES
    4.
    发明申请
    A METHOD OF ETCHING FERROELECTRIC DEVICES 审中-公开
    一种蚀刻电介质器件的方法

    公开(公告)号：WO2004077541A2

    公开(公告)日：2004-09-10

    申请号：PCT/SG2004000034

    申请日：2004-02-09

    Applicant: INFINEON TECHNOLOGIES AG ,  EGGER ULRICH ,  ZHUANG HAOREN ,  BRUCHHAUS RAINER

    Inventor： EGGER ULRICH ,  ZHUANG HAOREN ,  BRUCHHAUS RAINER

    IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3213

    CPC classification number: H01L21/32139 ,  H01L21/31122 ,  H01L21/32136 ,  H01L28/55 ,  H01L28/60

    Abstract: A method of etching a ferroelectric device (100) having a ferroelectric layer (112) between a top and a bottom electrode (114, 108) is disclosed herein. Hardmasks (116, 118) are deposited on the top electrode (114), two or more hardmasks being spaced apart by narrow first regions (115) and spaced apart from other hardmasks by wider second regions (117). The top electrode (114) and ferroelectric layer (112) are then etched to pattern the top electrode (114) thus forming capacitors (102, 104), and the bottom electrode (108) is etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode (108), but in the second regions the bottom electrode is severed. To pattern the bottom electrode (108), a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.

    Abstract translation: 本文公开了一种在顶部电极和底部电极（114,108）之间蚀刻具有铁电体层（112）的铁电体元件（100）的方法。 硬掩模（116,118）沉积在顶部电极（114）上，两个或更多个硬掩模由窄的第一区域（115）间隔开，并且由较宽的第二区域（117）与其它硬掩模隔开。 然后蚀刻顶部电极（114）和铁电体层（112）以对顶部电极（114）进行图案，从而形成电容器（102,104），并且通过其中第二区域 蚀刻比第二区域更缓慢。 那些在它们之间具有第一区域的电容器具有共同的底部电极（108），但是在第二区域中，底部电极被切断。 为了对底部电极（108）进行图案化，其后采用基于CO的化学物质的氟基化学物质用于两步蚀刻工艺。

    8.
    发明专利
    未知

    公开(公告)号：DE102004042174A1

    公开(公告)日：2006-03-02

    申请号：DE102004042174

    申请日：2004-08-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRUCHHAUS RAINER ,  GUTSCHE MARTIN ,  PINNOW CAY-UWE

    IPC: G11C11/22 ,  H01L21/316 ,  H01L27/105

    Abstract: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

Patent Agency Ranking