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    2.
    发明专利
    未知

    公开(公告)号：DE10230715B4

    公开(公告)日：2006-12-21

    申请号：DE10230715

    申请日：2002-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BONART DIETRICH ,  VOIGT PETER ,  ENDERS GERHARD

    IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786

    Abstract: The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably reduce or entirely avoid negative effects that normally result from the production of insulation structures between the vertical transistors. In particular, broadening of the gate oxide at the edge of the gate electrode can be prevented, and the edge of the gate electrode can be influenced deliberately. This allows vertical transistors to be produced having a current/voltage characteristic that can be adjusted specifically. In particular, vertical transistors can be produced having a pronounced corner effect.

    8.
    发明专利
    未知

    公开(公告)号：DE10212932B4

    公开(公告)日：2006-02-09

    申请号：DE10212932

    申请日：2002-03-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： VOIGT PETER ,  ENDERS GERHARD

    IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/94

    Abstract: A trench cell for use in a DRAM array includes a vertical selection transistor of a first conductivity type at the-seen in the bit line direction-first side of the trench hole, a blocking doping region near the surface, of a second conductivity type, is provided adjacent to the trench hole, the blocking doping region lying opposite the vertical selection transistor. As a result, leakage currents can be avoided and, in addition, the trench cells can be disposed at a shorter distance from one another.

    9.
    发明专利
    未知

    公开(公告)号：DE10260770B4

    公开(公告)日：2005-10-27

    申请号：DE10260770

    申请日：2002-12-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

    IPC: G11C11/404 ,  H01L21/334 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108

    Abstract: A memory cell comprises a trench capacitor with electrodes (9,11) and a dielectric layer (10) in the base with a vertical select transistor (TR) above this with a channel connecting electrode and a bit line (BL). The channel partly encloses the trench hole and the corresponding word line (WL) at least partly encloses the channel. Independent claims are also included for the following: (a) a memory cell arrangement as above;and (b) a production process for the above

    10.
    发明专利
    未知

    公开(公告)号：DE10324448B3

    公开(公告)日：2005-02-03

    申请号：DE10324448

    申请日：2003-05-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ENDERS GERHARD ,  VOIGT PETER ,  SCHNEIDER HELMUT

    IPC: H01L21/28 ,  H01L21/336

    Abstract: A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at least one cutout in the at least one sacrificial layer for uncovering the semiconductor substrate; forming a sidewall spacer over the sidewalls of the at least one sacrificial layer in the at least one cutout; forming a gate dielectric on the semiconductor substrate in the cutout; providing a gate electrode in the at least one cutout in the at lest one sacrificial layer; and removing the at least one sacrificial layer for the uncovering the gate electrode surrounded by the sidewall spacer. A semiconductor device is also provided.

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