公开(公告)号：DE10058782A1

公开(公告)日：2002-06-06

申请号：DE10058782

申请日：2000-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239 ,  H01L27/105

Abstract: A chain Fe-RAM/CFRAM with four single memory cells (S0-S3) connects via an inserted chain select transistor or a block select transistor (BS) to a bit line device (BL) on the input side and to a plate line device (PL) on the output side. The chain/block select transistor selects each chain made up of the memory cells. Within the chain the single memory cells are actuated by means of word line devices (WL0-WL3) and corresponding cell select transistors (T0-T3). An Independent claim is also included for a capacitor structure.

公开(公告)号：DE10056830A1

公开(公告)日：2002-05-29

申请号：DE10056830

申请日：2000-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14

Abstract: The invention relates to an integrated magnetoresistive semiconductor memory system, in which n memory cells that comprise two magnetic layers (WML, HML), each separated by a thin dielectric barrier (TL), and associated word lines (WL) and bit lines (BL) that cross one another are vertically stacked in n layers (L1, L2, L3, L4). The system further comprises a decoding circuit for selecting one of the n memory layers (L1 - L4). Said decoding circuit, on both ends of a word line (WL) or a bit line (BL), is provided with one arrangement each that consists of n layer selecting transistors (N0 - N3, N4 - N7) for selecting one of the n memory layers (L1 - L4), and with a line selection transistor (P0, P1) for selecting the respective horizontal word line or bit line (WL or BL) on which a voltage (V) is to be impressed.

公开(公告)号：DE10050702A1

公开(公告)日：2002-04-25

申请号：DE10050702

申请日：2000-10-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS

IPC: G06F12/06 ,  G11C5/00 ,  G11C7/00 ,  G11C11/407 ,  H01R13/64 ,  G06F12/00

Abstract: A memory module system has a first module card (1) with DRAM components (2) and an ECC element (3). A second module card also has DRAM components. The first module card is plugged into a first plug-in base and the second module card into a second plug-in base. A sentinel flag element (7) ensures definite coordination of module cards and plug-in bases.

公开(公告)号：DE10038925A1

公开(公告)日：2002-03-14

申请号：DE10038925

申请日：2000-08-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C11/14 ,  G11C8/08 ,  G11C8/10 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: An electronic driver connection for a memory matrix wordlines comprises a driver source (2) having many coded outputs (IV0 - IV3, V0). Many wordline switches (N1-16, P1-8) are controllable by a control signal (SLNP;SLN1;SLN2) and switchably connect the drive source output to the word lines. Independent claims are also included for the following: (a) a memory device according to the above; and (b) a nonvolatile magnetic semiconductor memory for the above.

公开(公告)号：DE10016726A1

公开(公告)日：2001-10-18

申请号：DE10016726

申请日：2000-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: The method involves the use of a pre-charge step that coincides with each drive phase of a short circuit transistor and during which the selection transistors are blocked. After the selection of memory cells the drive phases of the corresp. short circuit transistors of the selected cells are terminated by a negative potential on the corresp. word line of each short circuit transistor.

公开(公告)号：DE60319696T2

公开(公告)日：2009-04-16

申请号：DE60319696

申请日：2003-06-04

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： MIYAKAWA TADASHI ,  TAKASHIMA DAISABURO ,  ROEHR THOMAS

IPC: G11C29/00 ,  G11C7/22

公开(公告)号：DE50210116D1

公开(公告)日：2007-06-21

申请号：DE50210116

申请日：2002-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  ROEHR THOMAS

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22

Abstract: An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving can thus be achieved and therefore the MRAM configuration is less expensive to manufacture and has a greater packing density. In addition, the MRAM configuration allows a rapid read access with a minimal area requirement.

公开(公告)号：DE10310779B4

公开(公告)日：2007-04-05

申请号：DE10310779

申请日：2003-03-12

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： TAKASHIMA DAISABURO ,  SHIRATAKE SHINICHIRO ,  JOACHIM HANS-OLIVER ,  ROEHR THOMAS

IPC: G11C11/22 ,  G11C5/14 ,  G11C7/02 ,  G11C7/22 ,  G11C8/08 ,  G11C16/02 ,  H01L21/8246 ,  H01L27/105

Abstract: A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.

公开(公告)号：DE10058782B4

公开(公告)日：2006-03-23

申请号：DE10058782

申请日：2000-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: H01L21/8239 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: In order to provide a particularly space-saving capacitor configuration in a memory device, a plurality of second electrode regions which are not in direct electrical contact with one another are formed on areas of a first electrode region covered by a dielectric material. During operation of the capacitor configuration, portions of the first electrode region form bottom electrodes which are connected by a connecting region, so that an additional connecting device for the bottom electrodes is not necessary.

公开(公告)号：DE102004041330B3

公开(公告)日：2006-03-16

申请号：DE102004041330

申请日：2004-08-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS

IPC: G11C13/00 ,  G11C8/00

Abstract: In a memory circuit having memory cells which are connected in series between a ground line PL and a bit line BL and in each case have a resistance memory element said element having a bipolar switching behavior having an anode electrode and a cathode electrode, and a drive transistor connected in parallel with the resistance memory element, the drive transistors of the memory cells in each case are connected to a word line in order to switch the drive transistor on and off in such a way that a current path is formed via the associated drive transistor in a non-activated state of a memory cell and a current path is formed via the associated resistance memory element in an activated state of a memory cell, a first changeover switch being arranged at one end and a second changeover switch at other ends of the series of memory cells in order alternately to produce a connection between the series-connected memory cells and the ground line and the bit line in a manner dependent on an applied address.