公开(公告)号：JP2002203388A

公开(公告)日：2002-07-19

申请号：JP2001331484

申请日：2001-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  LAMMERS STEFAN ,  GOGL DIETMAR ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for obstructing undesirable programming in a MRAM device so that disablement of programming owing to scattered magnetic field of a memory cell being adjacent to a selection memory cell can be surely and simply obstructed. SOLUTION: A current IBL2 flowing in a bit line BL2 generates a scattered magnetic field in a MTJ memory cell I3 in an intersection part of a bit line BL3 and a word line WL1. Then an adequate compensation current IBL3 is made to flow in the bit line BL3 to suppress influence of this scattered magnetic field, scattered magnetic field in the MTJ memory cell I3 can be canceled by compensation magnetic field generated by this compensation current IBL3.

公开(公告)号：JP2002164515A

公开(公告)日：2002-06-07

申请号：JP2001275812

申请日：2001-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM module structure wherein high packing density of memory cell sections is achieved. SOLUTION: This MRAM module structure is constituted of a plurality of memory cell sections (A, P). The respective memory cell sections (A, P) are constituted of memory arrays (A) having a plurality of memory cells (WML, TL, HML) and peripheral circuits (P) surrounding edges of the memory arrays (A). The peripheral circuits (P) surround the memory arrays (A) in such a manner that the respective memory cell sections (A, P) have a cross structure in a plane, essentially. The memory cell sections (A, P) are so nested in each other that the memory cell sections (A, P) are offset mutually on individual rows (1, 2, 3).

公开(公告)号：WO0239454A3

公开(公告)日：2002-12-19

申请号：PCT/EP0112622

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG ,  FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

Inventor： FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/15

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/16

Abstract: The form of the supply lines in a cell field made from a matrix of columned and lined supply lines of a plurality of magnetic memory cells is optimised by diverging from a quadratic cross-section of the supply lines so that the magnetic field component Bx of the writing currents arranged on the plane of the cell field is rapidly reduced at an increasing distance from the increasing point of intersection.

Abstract translation: 从列和行的矩阵一个建成的引线的形状导致的多个磁存储单元的单元阵列被偏离引线的方形横截面的优化，使得磁场分量从交叉点Bx的随着距离的增加躺在单元阵列平面中的写电流的足够快地 降低。

公开(公告)号：WO02059898A2

公开(公告)日：2002-08-01

申请号：PCT/DE0200207

申请日：2002-01-23

Applicant: INFINEON TECHNOLOGIES AG ,  FREITAG MARTIN ,  ROEHR THOMAS

Inventor： FREITAG MARTIN ,  ROEHR THOMAS

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22

CPC classification number: H01L27/228 ,  G11C11/16

Abstract: The invention relates to an MRAM arrangement in which the selection transistors (5) and the MTJ layer sequences (4) lie parallel to each other in a cell. A considerable space saving can thus be achieved.

Abstract translation: 本发明涉及，其中，选择晶体管（5）和所述MTJ层序列（4）位于细胞平行于彼此，一个MRAM阵列。 这实现了显著面积节省。

公开(公告)号：WO02067266A3

公开(公告)日：2002-10-17

申请号：PCT/DE0200255

申请日：2002-01-24

Applicant: INFINEON TECHNOLOGIES AG ,  FREITAG MARTIN ,  MIETHANER STEFAN ,  RABERG WOLFGANG

Inventor： FREITAG MARTIN ,  MIETHANER STEFAN ,  RABERG WOLFGANG

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/1675

Abstract: The invention relates to a method for writing in the magnetoresistive memory cells of a MRAM memory, wherein the write currents (IWL, IBL) are applied respectively onto a word line (WL) and a bit line (BL), a superposition of the magnetic fields generated by the write currents in each memory cell selected by the corresponding word lines and bits lines altering the direction of the magnetisation thereof. According to the inventive method, the write currents (IWL, IBL) are applied in a chronologically offset manner, to the corresponding word line (WL) and the bit line (BL) whereby the direction of magnetisation of the selected memory cell is rotated in several consecutive steps (a - h) in the desired direction for writing a logical "0" or "1".

Abstract translation: 本发明涉及一种方法，用于写入，其中写入电流的MRAM存储器的磁阻的存储器单元（I

公开(公告)号：DE10103313A1

公开(公告)日：2002-08-22

申请号：DE10103313

申请日：2001-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  ROEHR THOMAS

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22

Abstract: An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving can thus be achieved and therefore the MRAM configuration is less expensive to manufacture and has a greater packing density. In addition, the MRAM configuration allows a rapid read access with a minimal area requirement.

公开(公告)号：DE50210116D1

公开(公告)日：2007-06-21

申请号：DE50210116

申请日：2002-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  ROEHR THOMAS

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22

Abstract: An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving can thus be achieved and therefore the MRAM configuration is less expensive to manufacture and has a greater packing density. In addition, the MRAM configuration allows a rapid read access with a minimal area requirement.

公开(公告)号：DE10055936A1

公开(公告)日：2002-05-23

申请号：DE10055936

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  HOENIGSCHMID HEINZ

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14 ,  G11C11/15

Abstract: The device has magnetic memory cells at intersections of a cell field with a matrix of row and column lines. In a write operation the magnetic fields generated by write currents in the lines add at an optional intersection to enable demagnetization of the local memory cell. The shape of the lines is optimized so that the magnetic field component in the plane of the cell field decreases rapidly with increasing distance from the intersection.

公开(公告)号：DE10045042C1

公开(公告)日：2002-05-23

申请号：DE10045042

申请日：2000-09-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN ,  BOEHM THOMAS

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: Single memory cell fields from memory arrays (A) and peripheral circuits (P) assigned to these are interlaced into each other so that utilizing free corner surfaces in a cross-shaped structure produces a high packing density for a module structure. Rows (1-3) in an MRAM module structure are offset to each other so that in row 2, for example, the peripheral circuits bordering on rows 1 and 3 fit in exactly to the corner surfaces of the memory cell fields in rows 1 and 3.

公开(公告)号：DE50110560D1

公开(公告)日：2006-09-07

申请号：DE50110560

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

IPC: G11C11/00 ,  H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08

Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.