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公开(公告)号：AU2002317779A1
公开(公告)日：2002-12-16
申请号：AU2002317779
申请日：2002-06-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： JANSSEN NORBERT , ELBE ASTRID , SEDLAK HOLGER
Abstract: An inventive electronic circuit includes a controller for processing a processor task as well as an energy determination means for determining the energy available to the controller. A control means of the electronic circuit controls the controller depending on the energy available to the controller. An optimum utilization of the energy available and, thus, an optimization of the computing speed with maximum energy utilization is achieved by means of the energy control.
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公开(公告)号：DE10116871A1
公开(公告)日：2002-11-07
申请号：DE10116871
申请日：2001-04-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEDER UWE , SEDLAK HOLGER
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公开(公告)号：ES2174480T3
公开(公告)日：2002-11-01
申请号：ES98943695
申请日：1998-07-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POCKRANDT WOLFGANG , SEDLAK HOLGER , VIEHMANN HANS-HEINRICH
Abstract: The invention relates to a semiconductor memory having a non-volatile two-transistor memory cell which has an N-channel selection transistor and an N-channel memory transistor. The drive circuitry for the cell includes a P-channel transfer transistor. A transfer channel is connected to a row line leading to the memory cell. This enables the voltages required for programming to be obtained with relatively little technological complexity.
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公开(公告)号：DE10109220A1
公开(公告)日：2002-09-12
申请号：DE10109220
申请日：2001-02-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SEDLAK HOLGER , HERMANN GERWIN , KNIFFLER OLIVER
IPC: H01L23/522 , H01L23/58 , H01L27/08
Abstract: The invention relates to an integrated circuit comprising a supply potential connection, a reference potential connection and an energy storage capacitor which is wired up between said two connections. Said energy storage capacitor consists of two conductor tracks or sections of conductor track which are coupled to each other in a capacitive manner.
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公开(公告)号：DE10109562A1
公开(公告)日：2002-09-05
申请号：DE10109562
申请日：2001-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SEDLAK HOLGER , NOLLES JUERGEN , HARTLIEB HEIMO
Abstract: Computer has an workflow controller with a program counter and an instruction decoder (4) for generating single instruction steps for a command that is to be executed. An error correction device (7) is connected to the flow controller and associated with it is a monitoring device (10), an error store (11) and an error handler (12). The error store includes known instructions that lead to errors, while the monitoring device compares the next instruction to execute with the known error instructions and if there is an agreement activates the error handler so that it undertakes appropriate counter measures.
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Patent Agency Ranking
公开(公告)号：DE10102202A1
公开(公告)日：2002-08-08
申请号：DE10102202
申请日：2001-01-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： MAY CHRISTIAN , SEDLAK HOLGER
Abstract: A microprocessor circuit includes a control unit, a memory for free programming with at least one program having functions, a stack for buffer-storing data, a register bank having at least one register, and an auxiliary register that stores a number of bits, each of the bits being assigned to one of the registers of the register bank and indicating whether or not a respective register of the register bank contains information items.
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公开(公告)号：DE10061998A1
公开(公告)日：2002-07-18
申请号：DE10061998
申请日：2000-12-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ELBE ASTRID , JANSSEN NORBERT , SEDLAK HOLGER
Abstract: A cryptographic processor for performing operations for cryptographic applications comprises a plurality of coprocessors, each coprocessor having a control unit and an arithmetic unit, a central processing unit for controlling said plurality of coprocessors and a bus for connecting each coprocessor to the central processing unit. The central processing unit, the plurality of coprocessors and the bus are integrated an one single chip. The chip further comprises a common power supply terminal for feeding said plurality of coprocessors. By way of parallel connection of various coprocessors, there is obtained an the one hand an increase in throughput and an the other hand an improvement in security of the cryptographic processor with respect to attacks that are based an the evaluation of power profiles of the cryptographic processor, since power profiles of a least two coprocessors are superimposed. Furthermore, the cryptographic processor, by utilization of different coprocessors, may also be implemented as a multifunctional cryptographic processor so as to be suitable for a multiplicity of different cryptographic algorithms.
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公开(公告)号：AU2793002A
公开(公告)日：2002-06-24
申请号：AU2793002
申请日：2001-11-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ELBE ASTRID , JANSSEN NORBERT , SEDLAK HOLGER
Abstract: A cryptographic processor for performing operations for cryptographic applications comprises a plurality of coprocessors, each coprocessor having a control unit and an arithmetic unit, a central processing unit for controlling said plurality of coprocessors and a bus for connecting each coprocessor to the central processing unit. The central processing unit, the plurality of coprocessors and the bus are integrated an one single chip. The chip further comprises a common power supply terminal for feeding said plurality of coprocessors. By way of parallel connection of various coprocessors, there is obtained an the one hand an increase in throughput and an the other hand an improvement in security of the cryptographic processor with respect to attacks that are based an the evaluation of power profiles of the cryptographic processor, since power profiles of a least two coprocessors are superimposed. Furthermore, the cryptographic processor, by utilization of different coprocessors, may also be implemented as a multifunctional cryptographic processor so as to be suitable for a multiplicity of different cryptographic algorithms.
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公开(公告)号：DE10142155C1
公开(公告)日：2002-05-23
申请号：DE10142155
申请日：2001-08-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ELBE ASTRID , JANSSEN NORBERT , SEDLAK HOLGER , SEIFERT JEAN-PIERRE
Abstract: The invention relates to a method for modular multiplication of a multiplicand (C) with a multiplicator (M) using a module (N), whereby firstly l multiplication shift values are determined (10), using a multiplication forecast method using l blocks of adjacent multiplicator (M) positions. l Reduction shift values are then determined (13), using a reduction prediction method for the l blocks of multiplicator (M) positions. An intermediate result (Z), from a previous iteration step, the module (N), or a value derived from the module and the multiplicand (C) are processed (16) with the l multiplication shift values and the l reduction shift values to obtain the 2l+1 operands (17). The 2l+1 operands are combined by means of a multi-operand summator (18), to obtain an updated intermediate result (Z') for an iteration step, following the previous iteration step, whereby the iteration is continued until all the multiplicator positions (M) are used. Depending on the number of operands the number of cycles to be calculated may be reduced such that a more rapid calculation of the modular multiplication is possible without an increased hardware complexity.
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公开(公告)号：DE59802720D1
公开(公告)日：2002-02-21
申请号：DE59802720
申请日：1998-02-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SEDLAK HOLGER
Abstract: The electronic data-processing device has a processing unit which is connected to one or more memories via a bus. The processing unit has an encryption unit associated with it. One or more secret keys are stored in the one or more memories. All security-related data, and possibly other data as well, are stored in encrypted form in the memory or memories. A comparator compares the stored secret key with a keyword input by a user. The comparator drives a switching unit which in turn drives the encryption unit. Stored data are decrypted only if the comparison is positive.
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