公开(公告)号：US09691857B2

公开(公告)日：2017-06-27

申请号：US15197615

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L31/00 ,  H01L29/15 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/20 ,  H01L29/786 ,  H01L29/78 ,  B82Y10/00 ,  H01L23/66 ,  H01L27/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20170170318A1

公开(公告)日：2017-06-15

申请号：US15442087

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L29/51 ,  H01L29/08 ,  H01L29/267 ,  H01L29/207

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20250133822A1

公开(公告)日：2025-04-24

申请号：US19001219

申请日：2024-12-24

Applicant: Intel Corporation

Inventor： Nicole Thomas ,  Eric Mattson ,  Sudarat Lee ,  Scott B. Clendenning ,  Tobias Brown-Heft ,  I-Cheng Tung ,  Thoe Michaelos ,  Gilbert Dewey ,  Charles Kuo ,  Matthew Metz ,  Marko Radosavljevic ,  Charles Mokhtarzadeh

IPC: H10D84/85 ,  H01L21/02 ,  H01L21/28 ,  H10D30/01 ,  H10D30/67 ,  H10D30/69 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

公开(公告)号：US12266570B2

公开(公告)日：2025-04-01

申请号：US17133065

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Souvik Ghosh ,  Willy Rachmady ,  Ashish Agrawal ,  Siddharth Chouksey ,  Jessica Torres ,  Jack Kavalieros ,  Matthew Metz ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

公开(公告)号：US20240222483A1

公开(公告)日：2024-07-04

申请号：US18091211

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Kevin O’Brien ,  Chelsey Dorow ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Matthew Metz ,  Scott B. Clendenning ,  Chia-Ching Lin ,  Ande Kitamura ,  Mahmut Sami Kavrik

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/0257 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: A transistor structure includes a stack of nanoribbons spanning between terminals of the transistor. Ends of the nanoribbons include silicon, and channel regions between the ends include a transition metal and a chalcogen. A gate structure over the channel regions includes an insulator between the channel regions and a gate electrode material. Contact regions may be formed by modifying portions of the channel regions by adding a dopant to, or altering the crystal structure of, the channel regions. The transistor structure may be in an integrated circuit device.

公开(公告)号：US20240222461A1

公开(公告)日：2024-07-04

申请号：US18091201

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Ande Kitamura ,  Carl H. Naylor ,  Kevin O'Brien ,  Kirby Maxey ,  Chelsey Dorow ,  Ashish Verma Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz ,  Chia-Ching Lin ,  Sudarat Lee ,  Mahmut Sami Kavrik ,  Carly Rogan ,  Paul Gutwin

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/443 ,  H01L23/528 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/775

CPC classification number: H01L29/45 ,  H01L21/02568 ,  H01L21/443 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/775

Abstract: A transistor in an integrated circuit (IC) die includes source and drain terminals having a bulk material enclosed by a liner material. A nanoribbon channel region couples the source and drain terminals. The nanoribbon may include a transition metal and a chalcogen. The liner material may contact ends and upper and lower surfaces of the nanoribbon. The transistor may be in an interconnect layer. The source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the IC die.

公开(公告)号：US20240222113A1

公开(公告)日：2024-07-04

申请号：US18091279

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Kevin OBrien ,  Chelsey Dorow ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Matthew Metz ,  Scott B. Clendenning ,  Mahmut Sami Kavrik ,  Chia-Ching Lin ,  Ande Kitamura

IPC: H01L21/02 ,  H01L21/04 ,  H01L23/31

CPC classification number: H01L21/02568 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/045 ,  H01L23/3171

Abstract: Integrated circuit (IC) structures comprising transistors with metal chalcogenide channel material synthesized on a workpiece comprising a Group IV crystal. Prior to synthesis of the metal chalcogenide material, a passivation material is formed over the Group IV crystal to limit exposure of the substrate to the growth precursor gas(es) and thereby reduce a quantity of chalcogen species subsequently degassed from the workpiece. The passivation material may be applied to the front side, back side, and/or edge of a workpiece. The passivation material may be sacrificial or retained as a permanent feature of an IC structure. The passivation material may be advantageously amorphous and/or a compound comprising at least one of a metal or nitrogen that is good diffusion barrier and thermally stable at the metal chalcogenide synthesis temperatures.

公开(公告)号：US20240112714A1

公开(公告)日：2024-04-04

申请号：US17957591

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Christopher Neumann ,  Brian Doyle ,  Sou-Chi Chang ,  Bernal Granados Alpizar ,  Sarah Atanasov ,  Matthew Metz ,  Uygar Avci ,  Jack Kavalieros ,  Shriram Shivaraman

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

CPC classification number: G11C11/221 ,  H01L27/11507 ,  H01L28/55

Abstract: A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.

公开(公告)号：US11862715B2

公开(公告)日：2024-01-02

申请号：US17745822

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US11756998B2

公开(公告)日：2023-09-12

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0684 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.