公开(公告)号：EP2479788A3

公开(公告)日：2015-02-25

申请号：EP12164665.7

申请日：2007-12-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kaneko, Kentaro ,  Kodani, Kotaro ,  Nakamura, Junichi ,  Kobayashi, Kazuhiro

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H05K1/113 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring substrate (10) has a pad (12) formed from a plurality of metal layers (26, 27, 28) and a via (13,17,29) connected to the pad. The plurality of metal layers have a metal layer (26) exposed through the wiring substrate, and a first metal layer (27) which is interposed between the metal layer and via and which prevents diffusion of metal included in the via into the metal layer. A second metal layer (28) which is less subject to oxidation than the first metal layer (27) is provided between the via (13) and the first metal layer, and the via is connected to a roughened surface of the second metal layer. An insulation layer (11) covers the side surfaces of the pad and the roughened surface of the second metal layer except for a region of the surface exposed by an opening section (25) in which the via is provided.

公开(公告)号：EP2759622B1

公开(公告)日：2018-11-28

申请号：EP12834344.9

申请日：2012-09-10

Applicant: JX Nippon Mining & Metals Corporation

Inventor： SHIBUYA, Yoshitaka ,  FUKAMACHI, Kazuhiko ,  KODAMA, Atsushi

IPC: B32B15/01 ,  C22C5/06 ,  C22C5/08 ,  C22C5/10 ,  C22C9/02 ,  C22C9/04 ,  C22C13/02 ,  C22C19/03 ,  C22C19/07 ,  C22C22/00 ,  C22C27/06 ,  C22C38/00 ,  C25D5/10 ,  C25D5/12 ,  C25D5/50 ,  C23C18/16 ,  H05K3/24 ,  H01B1/02 ,  C25D3/12 ,  C25D3/20 ,  C25D3/30 ,  C25D3/38 ,  C25D3/46 ,  C25D3/50 ,  C25D3/56 ,  C25D3/62 ,  C25D3/64 ,  H01R13/03 ,  H05K1/11

CPC classification number: H01B1/02 ,  B32B15/01 ,  B32B15/018 ,  C22C5/06 ,  C22C5/08 ,  C22C5/10 ,  C22C9/00 ,  C22C9/02 ,  C22C9/04 ,  C22C13/00 ,  C22C13/02 ,  C22C19/03 ,  C22C19/07 ,  C22C22/00 ,  C22C27/06 ,  C22C38/00 ,  C23C18/1651 ,  C23C18/1692 ,  C25D3/12 ,  C25D3/20 ,  C25D3/30 ,  C25D3/38 ,  C25D3/46 ,  C25D3/50 ,  C25D3/567 ,  C25D3/62 ,  C25D3/64 ,  C25D5/10 ,  C25D5/12 ,  C25D5/505 ,  H01R13/03 ,  H05K1/117 ,  H05K1/118 ,  H05K3/244 ,  H05K2201/0341 ,  Y10T428/12681 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12722

Abstract: There are provided a metal material for electronic component which has low insertability/extractability, low whisker formability, and high durability, and a method for manufacturing the metal material. The metal material 10 for electronic components has a base material 11, an A layer 14 constituting a surface layer on the base material 11 and formed of Sn, In or an alloy thereof, and a B layer 13 constituting a middle layer provided between the base material 11 and the A layer 14 and formed of Ag, Au, Pt, Pd, Ru, Rh, Os, Ir or an alloy thereof, wherein the surface layer (A layer) 14 has a thickness of 0.002 to 0.2 µm, and the middle layer (B layer) 13 has a thickness of 0.001 to 0.3 µm.

公开(公告)号：EP2732967A4

公开(公告)日：2015-02-18

申请号：EP12810573

申请日：2012-07-11

Applicant: NHK SPRING CO LTD

Inventor： YAMAUCHI YUICHIRO ,  HIRANO SATOSHI ,  SAITO SHINJI ,  HANAMACHI TOSHIHIKO

IPC: B32B15/04 ,  B05D1/12 ,  C04B37/02 ,  C23C24/04 ,  C23C28/02 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H05K1/03 ,  H05K3/14 ,  H05K3/38

CPC classification number: B32B15/04 ,  B05D1/12 ,  C04B37/026 ,  C04B2237/121 ,  C04B2237/126 ,  C04B2237/128 ,  C04B2237/34 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/346 ,  C04B2237/348 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/706 ,  C23C24/04 ,  C23C28/02 ,  C23C28/30 ,  H01L21/4846 ,  H01L23/3735 ,  H01L23/498 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/83447 ,  H01L2924/1305 ,  H01L2924/13055 ,  H05K1/0306 ,  H05K3/14 ,  H05K3/38 ,  H05K2201/0341 ,  H05K2201/0355 ,  H05K2203/1344 ,  Y10T428/12056 ,  H01L2924/014 ,  H01L2924/00

Abstract: When a laminated body having a metal film formed on a ceramic base member is manufactured by using a cold spraying method, a laminated body having a high adhesion strength between a ceramic and the metal film and a method of manufacturing such a laminated body are provided. The laminated body includes a ceramic base member 10 having an insulating property, an intermediate layer 50 including metal or alloy as a main component formed on a surface of the ceramic base member 10, and a metal film layer (a circuit layer 20 and a cooling fin 40) formed on a surface of the intermediate layer 50 by accelerating a powder of metal or alloy with a gas and spraying and depositing the powder on the surface of the intermediate layer 50 as the powder is in a solid state.

公开(公告)号：EP2759622A1

公开(公告)日：2014-07-30

申请号：EP12834344.9

申请日：2012-09-10

Applicant: JX Nippon Mining & Metals Corp.

Inventor： SHIBUYA, Yoshitaka ,  FUKAMACHI, Kazuhiko ,  KODAMA, Atsushi

IPC: C25D7/00 ,  B32B15/01 ,  B32B15/04 ,  C22C5/02 ,  C22C5/04 ,  C22C5/06 ,  C22C5/08 ,  C22C5/10 ,  C22C9/00 ,  C22C9/02 ,  C22C9/04 ,  C22C9/05 ,  C22C9/06 ,  C22C13/00 ,  C22C19/03 ,  C22C19/07 ,  C22C22/00 ,  C22C27/06 ,  C22C30/06 ,  C22C38/00

CPC classification number: H01B1/02 ,  B32B15/01 ,  B32B15/018 ,  C22C5/06 ,  C22C5/08 ,  C22C5/10 ,  C22C9/00 ,  C22C9/02 ,  C22C9/04 ,  C22C13/00 ,  C22C13/02 ,  C22C19/03 ,  C22C19/07 ,  C22C22/00 ,  C22C27/06 ,  C22C38/00 ,  C23C18/1651 ,  C23C18/1692 ,  C25D3/12 ,  C25D3/20 ,  C25D3/30 ,  C25D3/38 ,  C25D3/46 ,  C25D3/50 ,  C25D3/567 ,  C25D3/62 ,  C25D3/64 ,  C25D5/10 ,  C25D5/12 ,  C25D5/505 ,  H01R13/03 ,  H05K1/117 ,  H05K1/118 ,  H05K3/244 ,  H05K2201/0341 ,  Y10T428/12681 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12722

Abstract: There are provided a metal material for electronic component which has low insertability/extractability, low whisker formability, and high durability, and a method for manufacturing the metal material. The metal material 10 for electronic components has a base material 11, an A layer 14 constituting a surface layer on the base material 11 and formed of Sn, In or an alloy thereof, and a B layer 13 constituting a middle layer provided between the base material 11 and the A layer 14 and formed of Ag, Au, Pt, Pd, Ru, Rh, Os, Ir or an alloy thereof, wherein the surface layer (A layer) 14 has a thickness of 0.002 to 0.2 µm, and the middle layer (B layer) 13 has a thickness of 0.001 to 0.3 µm.

公开(公告)号：EP2506690A1

公开(公告)日：2012-10-03

申请号：EP11160014.4

申请日：2011-03-28

Applicant: Atotech Deutschland GmbH

Inventor： Matejat, Kai-Jens ,  Lamprecht, Sven ,  Ewert, Ingo

IPC: H05K3/24 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K3/3473 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/11424 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/243 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2203/054 ,  H05K2203/0577 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate (102) including a permanent resin layer (103) on top of at least one contact area (101) and a temporary resin layer (104) on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer (106) on the substrate surface and iii) electroplate a metal or metal alloy layer (107) onto the conductive layer.

Abstract translation: 描述了在基板上形成金属或金属合金层的方法，包括以下步骤：i）在至少一个接触区域（101）的顶部和临时树脂（101）之上提供包括永久性树脂层（103）的基板（102） 层（104），ii）使包括至少一个接触区域的整个基板区域与适于在基板表面上提供导电层（106）的溶液接触，以及iii）电镀金属或金属 合金层（107）到导电层上。

公开(公告)号：EP1930946A2

公开(公告)日：2008-06-11

申请号：EP07122244.2

申请日：2007-12-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kaneko, Kentaro ,  Kodani, Kotaro ,  Nakamura, Junichi ,  Kobayashi, Kazuhiro

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H05K1/113 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring substrate (10) has pads (12) formed from a plurality of metal layers (26,27,28) and vias (13,17,29) connected to the pads. The plurality of metal layers have a metal layer (26) exposed through the wiring substrate, and a first metal layer (27) which is interposed between the metal layer and the vias and which prevents diffusion of metal included in the vias into the metal layer. A second metal layer (28) which is less subject to oxidation than the first metal layer (27) is provided between the vias and the first metal layer (27), and the vias are connected to the second metal layer (28).

Abstract translation: 布线基板（10）具有由连接到焊盘的多个金属层（26,27,28）和通孔（13,17,29）形成的焊盘（12）。 所述多个金属层具有通过所述布线基板露出的金属层（26）和介于所述金属层与所述通路之间的第一金属层（27），并且防止所述通孔中包含的金属扩散到所述金属层 。 在通孔和第一金属层（27）之间设置有比第一金属层（27）更少受到氧化的第二金属层（28），并且通孔连接到第二金属层（28）。

公开(公告)号：EP0298422A3

公开(公告)日：1990-10-31

申请号：EP88110710.6

申请日：1988-07-05

Applicant: HITACHI, LTD.

Inventor： Toba, Ritsuji ,  Murakami, Kanji ,  Kawamoto, Mineo

IPC: H05K3/10 ,  H05K3/02

CPC classification number: H05K3/384 ,  H05K3/108 ,  H05K3/385 ,  H05K3/427 ,  H05K2201/0317 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1157

Abstract: In conducting wiring by masking the portion other than the portion to be wired of a metallic laminate (2) with a photoresist (6) for plating and subjecting only the portion to be wired to pattern plating (7), the provision of a noble metal layer (5) made of gold, platinum or the like, or a metallic layer (5) made of a metal having a larger ionization tendency than that of a metal used in the pattern plating (7) on the metallic layer constituting the undercoat of the photoresist (6) for plating enables the peeling of the resist (6) for plating to be prevented and excellent fine wiring to be conducted.

公开(公告)号：US12010794B2

公开(公告)日：2024-06-11

申请号：US17709492

申请日：2022-03-31

Applicant: IBIDEN CO., LTD.

Inventor： Satoru Kawai

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/11 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2203/043

Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and having openings exposing the conductor pads, respectively, and plating bumps formed on the conductor pads such that each of the plating bumps includes a base plating layer formed in a respective one of the openings of the solder resist layer, and a top plating layer formed on the base plating layer. The plating bumps are formed such that the base plating layer has an upper surface and a side surface including a portion protruding from the solder resist layer and having a rough surface and that the top plating layer has a hemispherical shape and is covering only the upper surface of the base plating layer.

公开(公告)号：US20180160528A1

公开(公告)日：2018-06-07

申请号：US15578484

申请日：2015-10-30

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Shigeru MICHIWAKI

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/14 ,  H05K3/00

CPC classification number: H05K1/0284 ,  H05K1/0326 ,  H05K1/09 ,  H05K3/0014 ,  H05K3/0023 ,  H05K3/14 ,  H05K3/181 ,  H05K3/389 ,  H05K3/426 ,  H05K2201/0129 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2203/072 ,  H05K2203/124 ,  H05K2203/1461

Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.

公开(公告)号：US09883586B2

公开(公告)日：2018-01-30

申请号：US14808275

申请日：2015-07-24

Applicant: TOPPAN PRINTING CO. LTD. ,  NATIONAL UNIVERSITY CORPORATION GUNMA UNIVERSITY

Inventor： Tetsuyuki Tsuchida ,  Toshikazu Okubo ,  Ikuo Shohji ,  Akihiro Hirata

IPC: H05K1/09 ,  H05K3/10 ,  B23K1/19 ,  B23K1/00 ,  C25D7/00 ,  B23K35/26 ,  C22C13/02 ,  H05K3/24 ,  B23K1/008

CPC classification number: H05K1/09 ,  B23K1/0008 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K35/262 ,  C22C13/02 ,  C25D7/00 ,  H01L2924/0002 ,  H05K3/10 ,  H05K3/244 ,  H05K2201/0341 ,  H05K2203/043 ,  H01L2924/00

Abstract: There is provided a wiring substrate including an electrode including Cu or a Cu alloy, a plating film having a film including at least Pd, formed on the electrode, and a solder which is bonded onto the plating film by heating, has a melting point of lower than 140° C., and includes Pd dissolved therein, a Pd concentrated layer being absent between the solder and the electrode.