公开(公告)号：US09210797B2

公开(公告)日：2015-12-08

申请号：US13985285

申请日：2013-07-01

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Li Chai

IPC: G02F1/1343 ,  H05K1/02 ,  G02F1/1345 ,  G02F1/1362

CPC classification number: H05K3/4644 ,  G02F1/1345 ,  G02F2001/13629 ,  H01L27/124 ,  H05K1/0213 ,  H05K3/06 ,  H05K3/22 ,  H05K3/4038 ,  H05K2201/0338 ,  H05K2201/0784

Abstract: Any one of the fan-out leads includes a first metal strip portion having a predetermined number, located on a glass substrate, disposed along an extension direction of the fan-out lead and is spaced apart; an insulation layer covering each of the first metal strip portion, and disposed with a first through hole and a second through hole; and a second metal strip portion located on the insulation layer and being contacted with each of the first metal strip portion by the first through hole and the second through hole. Wherein, the lengths of the first metal strip portions of the fan-out leads are gradually increased along the direction which is from the center to the edge of the fan shape such that impedances of the fan-out leads are consistent.

Abstract translation: 所述扇出引线中的任一个包括具有预定数量的第一金属带部分，位于玻璃基板上，沿着扇出引线的延伸方向设置并间隔开; 绝缘层，覆盖所述第一金属带部分中的每一个，并且设置有第一通孔和第二通孔; 以及第二金属带部分，位于所述绝缘层上并且通过所述第一通孔和所述第二通孔与所述第一金属带部分中的每一个接触。 其中扇出引线的第一金属带部分的长度沿着扇形的中心到边缘的方向逐渐增加，使得扇出引线的阻抗一致。

公开(公告)号：US20140374140A1

公开(公告)日：2014-12-25

申请号：US13985285

申请日：2013-07-01

Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.

Inventor： Li Chai

IPC: H05K1/02

CPC classification number: H05K3/4644 ,  G02F1/1345 ,  G02F2001/13629 ,  H01L27/124 ,  H05K1/0213 ,  H05K3/06 ,  H05K3/22 ,  H05K3/4038 ,  H05K2201/0338 ,  H05K2201/0784

Abstract: Any one of the fan-out leads includes a first metal strip portion having a predetermined number, located on a glass substrate, disposed along an extension direction of the fan-out lead and is spaced apart; an insulation layer covering each of the first metal strip portion, and disposed with a first through bole and a second through hole; and a second metal strip portion located on the insulation layer and being contacted with each of the first metal strip portion by the first through hole and the second through hole. Wherein, the lengths of the first metal strip portions of the fan-out leads are gradually increased along the direction which is from the center to the edge of the fan shape such that impedances of the fan-out leads are consistent.

Abstract translation: 所述扇出引线中的任一个包括具有预定数量的第一金属带部分，位于玻璃基板上，沿着扇出引线的延伸方向设置并间隔开; 绝缘层，覆盖所述第一金属带部分中的每一个，并且设置有第一通孔和第二通孔; 以及第二金属带部分，位于所述绝缘层上并且通过所述第一通孔和所述第二通孔与所述第一金属带部分中的每一个接触。 其中扇出引线的第一金属带部分的长度沿着扇形的中心到边缘的方向逐渐增加，使得扇出引线的阻抗一致。

公开(公告)号：US20130286644A1

公开(公告)日：2013-10-31

申请号：US13563738

申请日：2012-08-01

Applicant: CHIH-CHEN LAI

Inventor： CHIH-CHEN LAI

IPC: F21V21/00

CPC classification number: H05K1/167 ,  F21S4/20 ,  F21Y2103/10 ,  F21Y2115/10 ,  H05K1/0296 ,  H05K1/111 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09663 ,  H05K2201/10106 ,  Y02P70/611

Abstract: An LED light bar includes LED chips and a printed circuit board. A number of welding pads are disposed on the printed circuit board, and correspondingly connected to anodes and cathodes of the LED chips respectively. The welding pads connected to the anodes of the LED chips are connected by wire lines for connecting an anode of an electrical power source. The welding pads connected to the cathodes of the LED chips are connected by the wire lines for connecting a cathode of the electrical power source. The resistance of the wire lines connected to the LED chips increases from one near the electrical power source to the one far from the electrical power source. The resistance of the welding pads connected to the LED chips decreases from one near the electrical power source to the one far from the electrical power source.

Abstract translation: LED灯条包括LED芯片和印刷电路板。 多个焊盘设置在印刷电路板上，分别相应地连接到LED芯片的阳极和阴极。 连接到LED芯片的阳极的焊盘通过用于连接电源的阳极的线路连接。 连接到LED芯片的阴极的焊盘通过用于连接电源的阴极的电线连接。 连接到LED芯片的电线的电阻从电源附近的电阻增加到远离电源的电阻。 连接到LED芯片的焊盘的电阻从电源附近的电阻减小到远离电源的电阻。

公开(公告)号：US08174471B2

公开(公告)日：2012-05-08

申请号：US12330720

申请日：2008-12-09

Applicant: Hyun-Chul Kim ,  Jin-Cheol Hong

Inventor： Hyun-Chul Kim ,  Jin-Cheol Hong

IPC: G09G3/36

CPC classification number: G02F1/1345 ,  H01L27/124 ,  H01L2924/0002 ,  H05K1/117 ,  H05K2201/0784 ,  H05K2201/09727 ,  H01L2924/00

Abstract: An array substrate for a liquid crystal display device includes a substrate including a display area and a non-display area, the non-display area having a link area and a pad area, array elements in the display area on the substrate, first to nth pads in the pad area (n is a natural number), first to nth link lines in the link area and connected to the first to nth pads, respectively, wherein the first to (n/2−1)th link lines are symmetrical with the nth to (n/2+1)th link lines with respect to (n/2)th link line, the first to (n/2−1)th link lines have inclined portions, and the inclined portions of the first to kth link lines have decreasing widths and decreasing lengths toward the kth link line from the first link line, wherein k is larger than 1 and smaller than (n/2).

Abstract translation: 一种液晶显示装置用阵列基板，具备包括显示区域和非显示区域的基板，所述非显示区域具有连接区域和焊盘区域，所述基板的显示区域中的阵列元件，第一至第n 焊盘区域中的焊盘（n是自然数），分别在链路区域中的第一至第n个链路线并分别连接到第一至第n个焊盘，其中第一到第（n / 2-1）个链路线与 第（n / 2）个连接线相对于第（n / 2）个连接线，第一至第（n / 2-1）个连接线具有倾斜部分，并且第一至第 第k个链路线具有从第一链路线到第k个链路线的宽度减小和长度减小，其中k大于1且小于（n / 2）。

公开(公告)号：US07622384B2

公开(公告)日：2009-11-24

申请号：US12003299

申请日：2007-12-21

Applicant: Irving Memis

Inventor： Irving Memis

IPC: H01L21/60 ,  H01L21/441

CPC classification number: H05K1/181 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0248 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

Abstract: A method of making an electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. The method involves forming the line patterns in such a manner so as to reduce line skew.

Abstract translation: 一种制造电子封装的方法，该电子封装包括其上定位有至少两个电气部件的电路化基板。 该包装包括接触部位的图案，每个接触部位具有与其耦合的部件之一。 接触部位的图案依次通过一组导线相互电连接，导线基本上防止偏斜具有基本上相同的长度。 该方法包括以这样的方式形成线图案以便减少线偏移。

公开(公告)号：US07459780B2

公开(公告)日：2008-12-02

申请号：US11399344

申请日：2006-04-07

Applicant: Wan-Jung Chen

Inventor： Wan-Jung Chen

IPC: H01L23/48

CPC classification number: G02F1/1345 ,  G02F2201/12 ,  H05K1/0213 ,  H05K1/0265 ,  H05K1/167 ,  H05K2201/0326 ,  H05K2201/0352 ,  H05K2201/0784 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/10136

Abstract: This invention discloses a fan-out wire structure for use in a display panel of a display device. The fan-out wire structure comprises a first metal layer, a first insulation layer, and a second metal layer. The first insulation layer is formed on the first metal layer and the second metal layer is formed on the first insulation layer, and the first metal layer and the second metal layer are electrically connected by a conductive material, so as to modulate the resistance of the fan-out wire structure by modulating the length of the second metal layer and the conductive material.

Abstract translation: 本发明公开了一种用于显示装置的显示面板的扇出线结构。 扇出线结构包括第一金属层，第一绝缘层和第二金属层。 第一绝缘层形成在第一金属层上，第二金属层形成在第一绝缘层上，第一金属层和第二金属层通过导电材料电连接，以便调制电阻 通过调制第二金属层和导电材料的长度来实现扇出线结构。

公开(公告)号：US20060255460A1

公开(公告)日：2006-11-16

申请号：US11127160

申请日：2005-05-12

Applicant: Irving Memis

Inventor： Irving Memis

IPC: H01L23/48

CPC classification number: H05K1/181 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0248 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

Abstract: An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. A method of making the package is also provided, as is a circuitized substrate and an information handling system, the latter adapted for having one or more of the electronic packages as part thereof.

Abstract translation: 一种电子封装，其包括具有定位在其上的至少两个电气部件的电路化基板。 该包装包括接触部位的图案，每个接触部位具有与其耦合的部件之一。 接触部位的图案依次通过一组导线相互电连接，导线基本上防止偏斜具有基本上相同的长度。 还提供了制造包装的方法，电路化基板和信息处理系统也是如此，后者适于将一个或多个电子包装作为其一部分。

公开(公告)号：US09653213B2

公开(公告)日：2017-05-16

申请号：US14645357

申请日：2015-03-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang Soo Park ,  Min Cheol Park

IPC: H01G4/30 ,  H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H01G2/06 ,  H01G4/012 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/012 ,  H01G4/1227 ,  H05K1/0216 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/0784

Abstract: A multilayer ceramic capacitor may include a ceramic body having first to third dielectric layers, first and third internal electrodes disposed to be partially exposed to an upper surface of the ceramic body, second and fourth internal electrodes disposed to be partially exposed to a lower surface of the ceramic body, internal resistance electrodes disposed on the third dielectric layers and partially exposed to the upper surface of the ceramic body, first and third external electrodes disposed on the ceramic body to be connected to the first and third internal electrodes, second and fourth external electrodes disposed to be connected to the second and fourth internal electrodes. The first and third external electrodes are electrically connected to each other by the internal resistance electrodes.

公开(公告)号：US20170013707A1

公开(公告)日：2017-01-12

申请号：US15273110

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Benjamin B. LYON ,  Shih-Chang CHANG ,  Martin Paul GRUNTHANER

IPC: H05K1/02 ,  G06F3/041

CPC classification number: H05K1/0242 ,  G06F3/0412 ,  G06F3/0416 ,  G06F2203/04108 ,  G09G3/2092 ,  H05K1/0265 ,  H05K2201/0784 ,  H05K2201/09272 ,  H05K2201/09727 ,  Y10T29/49155

Abstract: The border routing of conductive traces in devices, such as displays, touch sensor panels, and touch screens, to improve border area space usage, thereby reducing device size, and to reduce trace resistance, thereby improving device operation, is disclosed. The conductive traces can form a staggered stair-step configuration in the device border area, in which the average widths of the traces can be different from each other and each trace can have segments with different widths. The conductive traces can be coupled to an active area of the device to transmit signals to and from the active area in accordance with a device operation. The varying widths can help improve the border area space usage, reduce trace resistance, and reduce the differences in resistance between traces.

Abstract translation: 公开了诸如显示器，触摸传感器面板和触摸屏等设备中导电迹线的边界布线，以改善边界区域空间的使用，从而减少设备尺寸，并降低走线电阻，从而改善器件的操作。 导电迹线可以在器件边界区域中形成交错的阶梯结构，其中迹线的平均宽度可以彼此不同，并且每个迹线可以具有不同宽度的段。 导电迹线可以耦合到设备的有效区域，以根据设备操作向有源区域发送信号和从有源区域发送信号。 变化的宽度可以帮助改善边界区域空间的使用，减少走线电阻，并减少迹线之间的电阻差异。

公开(公告)号：US20160057871A1

公开(公告)日：2016-02-25

申请号：US14918623

申请日：2015-10-21

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Li CHAI

IPC: H05K3/46 ,  H05K3/22 ,  H05K3/40 ,  H05K3/06

CPC classification number: H05K3/4644 ,  G02F1/1345 ,  G02F2001/13629 ,  H01L27/124 ,  H05K1/0213 ,  H05K3/06 ,  H05K3/22 ,  H05K3/4038 ,  H05K2201/0338 ,  H05K2201/0784

Abstract: A method for manufacturing an array substrate includes a step of forming a first metal layer on a glass substrate such that the first metal layer includes multiple first metal lines distributed as a fan shape, each of the first metal lines including a predetermined number of first metal strip portions that are spaced from each other and have an equal length; forming an insulation layer on the multiple first metal lines in such a way that portions of the insulation layer respectively covering the first metal strip portions are each provided with a first through hole and a second through hole formed therein; and forming a second metal layer on the insulation layer such that the second metal layer includes multiple second metal strip portions respectively in contact with the first metal strip portions of the first metal lines via the first through holes and the second through holes.

Abstract translation: 一种阵列基板的制造方法，其特征在于，在玻璃基板上形成第一金属层，使得所述第一金属层包含分散为扇形的多个第一金属线，所述第一金属线包含规定数量的第一金属 带状部分彼此间隔开并具有相等的长度; 在所述多个第一金属线上形成绝缘层，使得分别覆盖所述第一金属带部的所述绝缘层的各部分分别设置有形成在其中的第一通孔和第二通孔; 以及在所述绝缘层上形成第二金属层，使得所述第二金属层包括分别经由所述第一通孔和所述第二通孔与所述第一金属线的所述第一金属带部分接触的多个第二金属带部分。