公开(公告)号：US20160079204A1

公开(公告)日：2016-03-17

申请号：US14850589

申请日：2015-09-10

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Tomoshige Chikai ,  Kiminori Ishido ,  Takashi Nakamura ,  Hirokazu Honda ,  Hiroshi Demachi ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Takeshi Miyakoshi ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L24/96 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Abstract translation: 本发明的半导体装置的制造方法包括：准备包含形成在其中的电极的半导体晶片; 将形成在半导体芯片中的第一半导体元件和形成在半导体晶片中的电极电连接; 用第一绝缘树脂层填充半导体晶片和半导体芯片之间的间隙; 在半导体晶片上形成第二绝缘树脂层; 研磨第二绝缘树脂层和半导体芯片直到半导体芯片的厚度达到预定厚度; 在所述第二绝缘树脂层和所述半导体芯片上形成第一绝缘层; 在与填充有第一绝缘层和第二绝缘树脂层的开口的导电材料连接的第一绝缘层上形成线以露出电极; 并研磨半导体晶片直到半导体晶片的厚度达到预定厚度。

公开(公告)号：US20200035582A1

公开(公告)日：2020-01-30

申请号：US16592213

申请日：2019-10-03

Applicant: J-DEVICES CORPORATION

Inventor： Masao HIROBE

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/04 ,  H01L23/00

Abstract: There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate.

公开(公告)号：US10388625B2

公开(公告)日：2019-08-20

申请号：US15290557

申请日：2016-10-11

Applicant: J-DEVICES CORPORATION

Inventor： Minoru Kai

IPC: H01L21/68 ,  H01L21/67 ,  H01L23/00

Abstract: A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided.

公开(公告)号：US10157760B2

公开(公告)日：2018-12-18

申请号：US15600082

申请日：2017-05-19

Applicant: J-DEVICES CORPORATION

Inventor： Minoru Kai

IPC: H01L21/68 ,  H01L21/67 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683

Abstract: A semiconductor manufacturing apparatus comprises a stage connected to a vacuum generator to suction a semiconductor wafer including a plurality of semiconductor chips, a suction control unit connected to a connecting portion of the stage and the vacuum generator to control the connection of the stage and the vacuum generator, a pickup unit connected to a movement control unit simultaneously picking up the plurality of semiconductor chips, and a control unit controlling movement and rotation of the pickup unit and controlling the suction control unit, the control unit is connected to the movement control unit. The pickup unit converts an interval of the plurality of semiconductor chips to a predetermined pitch and holds the pitch. The pickup unit moves the plurality of semiconductor chips from the stage to mounting positions of a supporting substrate and simultaneously adheres the plurality of semiconductor chips at the mounting positions by the control unit.

公开(公告)号：US10096564B2

公开(公告)日：2018-10-09

申请号：US15481848

申请日：2017-04-07

Applicant: J-DEVICES CORPORATION

Inventor： Toshiyuki Inaoka ,  Atsuhiro Uratsuji

IPC: H01L21/44 ,  H01L23/00

Abstract: A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top surface thereof, forming a resin insulating layer covering the semiconductor device, forming an opening, exposing the external terminal, in the resin insulating layer, performing plasma treatment on a bottom surface of the opening, performing chemical treatment on the bottom surface of the opening after the plasma treatment, and forming a conductive body to be connected with the external terminal exposed in the opening.

公开(公告)号：US10079161B2

公开(公告)日：2018-09-18

申请号：US15884979

申请日：2018-01-31

Applicant: J-Devices Corporation

Inventor： Toshiyuki Inaoka ,  Yuichiro Yoshikawa ,  Atsuhiro Uratsuji ,  Katsushi Yoshimitsu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/367

CPC classification number: H01L21/4871 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15747

Abstract: An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.

公开(公告)号：US20170373012A1

公开(公告)日：2017-12-28

申请号：US15585659

申请日：2017-05-03

Applicant: J-Devices Corporation

Inventor： Toshiyuki INAOKA ,  Yuichiro YOSHIKAWA ,  Atsuhiro URATSUJI ,  Katsushi YOSHIMITSU

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/4871 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15747

Abstract: An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.

公开(公告)号：US20170365534A1

公开(公告)日：2017-12-21

申请号：US15625464

申请日：2017-06-16

Applicant: J-DEVICES CORPORATION

Inventor： Hirokazu MACHIDA ,  Kazuhiko KITANO

IPC: H01L23/14 ,  H01L21/56 ,  H01L23/00 ,  H01L23/544 ,  H01L23/552 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/142 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/552 ,  H01L24/03 ,  H01L24/04 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/02311 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/03914 ,  H01L2224/04105 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2924/0665

Abstract: A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.

公开(公告)号：US20170316998A1

公开(公告)日：2017-11-02

申请号：US15493231

申请日：2017-04-21

Applicant: J-DEVICES CORPORATION

Inventor： Hisakazu MARUTANI ,  Minoru KAI ,  Kazuhiko KITANO

IPC: H01L23/31 ,  H01L21/82 ,  H01L21/56 ,  H01L23/544 ,  H01L23/00

Abstract: A manufacturing method of a semiconductor package includes locating a plurality of semiconductor packages on a substrate, forming a resin insulating layer covering the plurality of semiconductor devices, forming grooves, in the resin insulating layer, enclosing each of the plurality of semiconductor devices and reaching the substrate, and irradiating the substrate with laser light in positional correspondence with the grooves to separate the plurality of semiconductor devices from each other.

公开(公告)号：US09418944B2

公开(公告)日：2016-08-16

申请号：US14739829

申请日：2015-06-15

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki Hashimoto ,  Yasuyuki Takehara

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/36 ,  H01L23/373 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0224 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.

Abstract translation: 半导体封装包括支撑衬底; 设置在所述支撑基板的主表面上的应力松弛层; 位于应力松弛层上的半导体器件; 覆盖半导体器件的封装材料，封装材料由与应力松弛层不同的绝缘材料形成; 穿过封装材料并电连接到半导体器件的线; 以及与该线路电连接的外部端子。 在支撑基板具有A的弹性模量的情况下，应力松弛层的弹性模量为B，封装材料在相同的温度条件下具有C的弹性模量，A> C> B或C> A的关系 > B。